Display device

ABSTRACT

A display device comprises a pixel which comprises emission areas, a first voltage wiring and a second voltage wiring, which are outside the emission areas of the pixel and extend in a first direction and a second direction crossing the first direction, first electrodes and second electrodes which are respectively in the emission areas and extend in one direction, light emitting elements which are on the first and second electrodes, first contact electrodes which contact the first electrodes and the light emitting elements, and second contact electrodes which contact the second electrodes and the light emitting elements, and a first electrode line which overlaps the first voltage wiring and is outside the emission areas and a second electrode line which overlaps the second voltage wiring and is outside the emission areas, wherein each of the first electrodes and the first electrode line is electrically connected to the first voltage wiring, and each of the second electrodes and the second electrode line is electrically connected to the second voltage wiring.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean PatentApplication No. 10-2020-0065039 filed on May 29, 2020 in the KoreanIntellectual Property Office, the entire content of which is hereinincorporated by reference.

BACKGROUND 1. Field

One or more embodiments of the present disclosure relate to a displaydevice.

2. Description of the Related Art

Display devices are becoming increasingly important with the developmentof multimedia. Accordingly, various types of display devices, such asorganic light emitting displays and/or liquid crystal displays, arebeing used.

A display device is a device for displaying an image and includes adisplay panel such as an organic light emitting display panel or aliquid crystal display panel. As a light emitting display panel, thedisplay panel may include light emitting elements such as light emittingdiodes (LEDs). For example, the LEDs may be organic light emittingdiodes (OLEDs) using an organic material as a fluorescent material, ormay be inorganic LEDs using an inorganic material as the fluorescentmaterial.

SUMMARY

One or more aspects of embodiments of the present disclosure provide adisplay device manufactured by a reduced number of processes by forminga wiring, to which a voltage is applied, using a conductive layer(positioned) under the wiring.

One or more aspects of embodiments of the present disclosure alsoprovide a display device in which alignment of light emitting elementsin an unwanted (undesirable) area during a manufacturing process can beprevented or reduced by placing the above wiring outside emission areas.

However, aspects of the present disclosure are not restricted to the oneset forth herein. The above and other aspects of the present disclosurewill become more apparent to one of ordinary skill in the art to whichthe present disclosure pertains by referencing the detailed descriptionof the present disclosure given below.

According to some embodiments of the present disclosure, a displaydevice comprises a pixel which comprises emission areas; a first voltagewiring and a second voltage wiring outside the emission areas of thepixel, and extending both in a first direction and a second directioncrossing the first direction; first electrodes and second electrodes inthe emission areas and extending in one direction; light emittingelements on the first electrodes and the second electrodes; firstcontact electrodes contacting the first electrodes and the lightemitting elements; second contact electrodes contacting the secondelectrodes and the light emitting elements; a first electrode lineoverlapping the first voltage wiring and being outside the emissionareas; and a second electrode line overlapping the second voltage wiringand being outside the emission areas, wherein the first electrodes andthe first electrode line are electrically connected to the first voltagewiring, and the second electrodes and the second electrode line areelectrically connected to the second voltage wiring.

The first voltage wiring may comprise a first wiring horizontal portionextending in the first direction, and a first wiring vertical portionextending in the second direction, and the second voltage wiring maycomprise a second wiring horizontal portion extending in the firstdirection, and a second wiring vertical portion extending in the seconddirection.

The first wiring vertical portion may be on a different conductive layerthan the first wiring horizontal portion, and the second wiring verticalportion may be on a different conductive layer than the second wiringhorizontal portion.

The display device may further comprise a first wiring contact hole atan intersection of the first wiring horizontal portion and the firstwiring vertical portion; and a second wiring contact hole at anintersection of the second wiring horizontal portion and the secondwiring vertical portion.

The first wiring vertical portion may be on a side of the emission areasin the first direction, the second wiring vertical portion may be onanother side of the emission areas in the first direction, the secondwiring horizontal portion may be on a side of the emission areas in thesecond direction, and the first wiring horizontal portion may be onanother side of the emission areas in the second direction.

The first electrode line may overlap the first wiring vertical portionin a thickness direction of the display device, the second electrodeline may overlap the second wiring vertical portion in the thicknessdirection, and the second electrodes may be directly connected to thesecond electrode line.

The first electrodes and the second electrodes may extend in the firstdirection, and the first electrodes may be spaced apart from the firstelectrode line, and may be electrically connected to the first voltagewiring through a first electrode contact hole.

The display device may further comprise a first conductive patternoverlapping the first wiring vertical portion and connected to the firstwiring vertical portion, and a second conductive pattern overlapping thesecond wiring vertical portion and connected to the second wiringvertical portion, wherein the second electrode line may contact thesecond conductive pattern through a second electrode contact holeoverlapping the second conductive pattern, and the first electrode linemay contact the first conductive pattern through a third electrodecontact hole overlapping the first conductive pattern.

The first electrode line may comprise a first electrode stem portionextending in the second direction, and a first electrode branch portionbranching from the first electrode stem portion in the first direction;the second electrode line may comprise a second electrode stem portionextending in the second direction, and a second electrode branch portionbranching from the second electrode stem portion in the first direction;and the first electrode branch portion and the second electrode branchportion may respectively overlap the first wiring horizontal portion andthe second wiring horizontal portion in the thickness direction.

The first electrodes and the second electrodes may extend in the seconddirection, the second electrodes may be directly connected to the secondelectrode branch portion, and the first electrodes may be spaced apartfrom the first electrode branch portion.

The display device may further comprise cut areas spaced apart from theemission areas in the one direction in which the first electrodes andthe second electrodes extend, wherein the first electrodes and the firstelectrode line may be spaced apart with the cut areas therebetween.

The display device may further comprise first banks in the emissionareas and extending in the one direction in which the first electrodesand the second electrodes extend; and a second bank surrounding theemission areas, wherein the first voltage wiring and the second voltagewiring may overlap the second bank in the thickness direction.

The emission areas may comprise a first emission area, a second emissionarea, and a third emission area spaced apart from each other, the firstelectrodes and the second electrodes may be respectively in the firstemission area, the second emission area, and the third emission area,and the second electrodes that are respectively in the emission areasmay be directly connected to the same second electrode line.

According to some embodiments of the present disclosure, a displaydevice comprises pixels arranged in a first direction in pixel rows, andin a second direction in pixel columns, the second direction crossingthe first direction, the pixels comprising emission areas; a firstvoltage wiring and a second voltage wiring between the pixel columns andthe pixel rows, and extending in the first direction and the seconddirection; a first electrode line overlapping the first voltage wiringand connected to the first voltage wiring; and a second electrode lineoverlapping the second voltage wiring and connected to the secondvoltage wiring; first electrodes and second electrodes in the emissionareas of the pixels and extending in one direction; and light emittingelements having first ends respectively on the first electrodes, andsecond ends respectively on the second electrodes, wherein the firstelectrodes are spaced apart from the first electrode line, the secondelectrodes are connected to the second electrode line, and the pixelscomprise first type pixels in which the first ends of the light emittingelements face a first side of the first direction, and the firstelectrodes are spaced apart from the second electrodes in the firstdirection.

The first type pixels may be in the second direction in a first pixelcolumn, and the pixels may further comprise second type pixels in asecond pixel column, in which the first ends of the light emittingelements face a second side of the first direction, the second sidefacing oppositely away from the first side of the first direction, thesecond type pixels being symmetrical to the first type pixels inarrangement of the first electrodes and the second electrodes withrespect to a first imaginary line extending in the second direction.

The pixels may further comprise third type pixels in which the firstends of the light emitting elements face the first side of the firstdirection, the third type pixels being symmetrical to the first typepixels in arrangement of the first electrodes and the second electrodeswith respect to a second imaginary line extending in the firstdirection; and fourth type pixels in which the first ends of the lightemitting elements face the second side of the first direction, thefourth type pixels being symmetrical to the second type pixels inarrangement of the first electrodes and the second electrodes withrespect to the second imaginary line extending in the first direction.

The first electrodes of the first type pixels and of the second typepixels may be respectively side by side in the second direction with thefirst electrodes of the third type pixels and of the fourth type pixels.

The first type pixels and the third type pixels may alternate along thesecond direction in the first pixel column, and the second type pixelsand the fourth type pixels may alternate along the second direction inthe second pixel column.

The first type pixels and the fourth type pixels may alternate along thesecond direction in the first pixel column, and the second type pixelsand the third type pixels may alternate along the second direction inthe second pixel column.

The first type pixels and the fourth type pixels may alternate along thesecond direction in the first pixel column and the second pixel column.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and features of the present disclosure willbecome more apparent by describing in more detail some embodimentsthereof with reference to the attached drawings, in which:

FIG. 1 is a schematic plan view of a display device according to someembodiments;

FIG. 2 is a schematic layout view of wirings included in the displaydevice according to some embodiments;

FIG. 3 is an equivalent circuit diagram of one subpixel according tosome embodiments;

FIG. 4 is a schematic plan view of wirings in one pixel of the displaydevice according to some embodiments;

FIG. 5 is a layout view of a plurality of conductive layers included inone pixel of the display device according to some embodiments;

FIG. 6 is a layout view illustrating the arrangement of a firstconductive layer, a second conductive layer, and a semiconductor layerincluded in one pixel of the display device according to someembodiments;

FIG. 7 is a schematic plan view of a plurality of electrodes and aplurality of banks included in one pixel of the display device accordingto some embodiments;

FIG. 8 is a cross-sectional view taken along lines Q1-Q1′, Q2-Q2′ andQ3-Q3′ of FIG. 7;

FIG. 9 is a cross-sectional view taken along lines Q4-Q4′, Q5-Q5′ andQ6-Q6′ of FIG. 7;

FIG. 10 is a schematic view illustrating the arrangement of voltagewirings, electrodes, and electrode lines in one pixel of the displaydevice according to some embodiments;

FIG. 11 is a cross-sectional view taken along lines Q7-Q7′ and Q8-Q8′ ofFIG. 10;

FIG. 12 is a schematic view illustrating the arrangement of the voltagewirings and the electrode lines in a plurality of pixels of the displaydevice according to some embodiments;

FIG. 13 is a schematic view of a light emitting element according tosome embodiments;

FIGS. 14 through 16 are plan views sequentially illustrating acts of aprocess of manufacturing the display device according to someembodiments;

FIG. 17 is a schematic plan view of a plurality of electrodes and aplurality of banks included in one pixel of a display device accordingto some embodiments;

FIGS. 18 and 19 are plan views illustrating some acts of a process ofmanufacturing the display device of FIG. 17;

FIG. 20 is a schematic plan view of a plurality of electrodes and aplurality of banks included in one pixel of a display device accordingto some embodiments;

FIG. 21 is a schematic plan view of a plurality of electrodes and aplurality of banks included in one pixel of a display device accordingto some embodiments;

FIGS. 22 through 25 are schematic views illustrating the arrangement ofvoltage wirings and electrode lines in a plurality of pixels of displaydevices according to embodiments;

FIG. 26 is a schematic plan view of a plurality of electrodes and aplurality of banks included in one pixel of a display device accordingto some embodiments; and

FIG. 27 is a cross-sectional view taken along line Q9-Q9′ of FIG. 26.

DETAILED DESCRIPTION

The present disclosure will now be described more fully hereinafter withreference to the accompanying drawings, in which some embodiments of thepresent disclosure are shown. The disclosed embodiments may, however, beembodied in different forms and should not be construed as limited tothe embodiments set forth herein. Rather, these embodiments are providedso that this disclosure will be thorough and complete, and will fillyconvey the scope of the disclosure to those skilled in the art.

It will also be understood that when a layer is referred to as being“on” another layer or substrate, it can be directly on the other layeror substrate (without any intervening layers therebetween), orintervening layers may also be present. The same reference numbersindicate the same components throughout the specification.

It will be understood that, although the terms “first,” “second,” etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are only used to distinguishone element from another element. For instance, a first elementdiscussed below could be termed a second element without departing fromthe teachings of the present disclosure. Similarly, the second elementcould also be termed the first element.

The term “and/or” includes one or more combinations which may be definedby relevant elements. Expressions such as “at least one of,” “one of,”and “selected from,” when preceding a list of elements, modify theentire list of elements and do not modify the individual elements of thelist. Further, the use of “may” when describing embodiments of thepresent disclosure refers to “one or more embodiments of the presentdisclosure.”

As used herein, the terms “use,” “using,” and “used” may be consideredsynonymous with the terms “utilize,” “utilizing,” and “utilized,”respectively.

In addition, the terms “substantially,” “about,” and similar terms areused as terms of approximation and not as terms of degree, and areintended to account for the inherent deviations in measured orcalculated values that would be recognized by those of ordinary skill inthe art.

Also, any numerical range recited herein is intended to include allsub-ranges of the same numerical precision subsumed within the recitedrange. For example, a range of “1.0 to 10.0” is intended to include allsubranges between (and including) the recited minimum value of 1.0 andthe recited maximum value of 10.0, that is, having a minimum value equalto or greater than 1.0 and a maximum value equal to or less than 10.0,such as, for example, 2.4 to 7.6. Any maximum numerical limitationrecited herein is intended to include all lower numerical limitationssubsumed therein and any minimum numerical limitation recited in thisspecification is intended to include all higher numerical limitationssubsumed therein. Accordingly, Applicant reserves the right to amendthis specification, including the claims, to expressly recite anysub-range subsumed within the ranges expressly recited herein.

The device and/or any other relevant devices or components according toembodiments of the present disclosure described herein may beimplemented utilizing any suitable hardware, firmware (e.g. anapplication-specific integrated circuit), software, or a combination ofsoftware, firmware, and hardware. For example, the various components ofthe device may be formed on one integrated circuit (IC) chip or onseparate IC chips. Further, the various components of the device may beimplemented on a flexible printed circuit film, a tape carrier package(TCP), a printed circuit board (PCB), or formed on one substrate.Further, the various components of the device may be a process orthread, running on one or more processors, in one or more computingdevices, executing computer program instructions and interacting withother system components for performing the various functionalitiesdescribed herein. The computer program instructions are stored in amemory which may be implemented in a computing device using a standardmemory device, such as, for example, a random access memory (RAM). Thecomputer program instructions may also be stored in other non-transitorycomputer readable media such as, for example, a CD-ROM, flash drive, orthe like. Also, a person of skill in the art should recognize that thefunctionality of various computing devices may be combined or integratedinto a single computing device, or the functionality of a particularcomputing device may be distributed across one or more other computingdevices without departing from the scope of the disclosed embodiments.

Hereinafter, embodiments will be described with reference to theattached drawings.

FIG. 1 is a schematic plan view of a display device 10 according to someembodiments.

In the present specification, “above,” “top,” and “upper surface”indicate an upward direction from the display device 10, that is, adirection along a third direction DR3; and “under,” “bottom,” and “lowersurface” indicate a downward direction from the display device 10, thatis, a direction opposite of the third direction DR3. In someembodiments, “left,” “right,” “upper,” and “lower” indicate directionswhen the display device 10 is seen in plan view. For example, “left”indicates a direction along a first direction DR1, “right” indicates adirection opposite of the first direction DR1, “upper” indicates adirection along a second direction DR2, and “lower” indicates adirection opposite of the second direction DR2.

Referring to FIG. 1, the display device 10 can display moving imagesand/or still images. The display device 10 may refer to any suitableelectronic device that provides a display screen. Examples of thedisplay device 10 may include televisions, notebook computers, monitors,billboards, the Internet of things (IoT), mobile phones, smartphones,tablet personal computers (PCs), electronic watches, smart watches,watch phones, head mounted displays, mobile communication terminals,electronic notebooks, electronic books, portable multimedia players(PMPs), navigation devices, game machines, digital cameras andcamcorders, all of which provide a display screen.

The display device 10 includes a display panel that provides a displayscreen. Examples of the display panel include inorganic light emittingdiode display panels, organic light emitting display panels, quantum dotlight emitting display panels, plasma display panels, and field emissiondisplay panels, without limitation. Some embodiments in which aninorganic light emitting diode display panel is applied as an example ofthe display panel will be described below, but the present disclosure isnot limited to this example, and other display panels can also beapplied as long as the same technical spirit is applicable.

The shape of the display device 10 can be variously suitably modified.For example, the display device 10 may have various suitable shapes suchas a horizontally long rectangle, a vertically long rectangle, a square,a quadrangle with rounded corners (vertices), other polygons, and/or acircle. The shape of a display area DPA of the display device 10 mayalso be similar to the overall shape of the display device 10. In FIG.1, each of the display device 10 and the display area DPA is in theshape of a horizontally long rectangle.

The display device 10 may include the display area DPA and a non-displayarea NDA. The display area DPA may be an area where a screen (image) canbe displayed, and the non-display area NDA may be an area where noscreen (image) is displayed. The display area DPA may also be referredto as an active area, and the non-display area NDA may also be referredto as an inactive area. The display area DPA may generally(substantially) occupy a center of the display device 10.

The display area DPA may include a plurality of pixels PX. The pixels PXmay be arranged in a matrix orientation. Each of the pixels PX may berectangular or square in plan view. However, the present disclosure isnot limited thereto, and each of the pixels PX may have a rhombic planarshape having each side inclined with respect to a direction (e.g., withrespect to DR1 and/or DR2 directions). The pixels PX may be alternatelyarranged in either a stripe or PenTile®/PENTILE® fashion or pattern(PENTILE® is a registered trademark owned by Samsung Display Co., Ltd.).In some embodiments, each of the pixels PX may include one or more lightemitting elements ED which emit light of a specific (or set) wavelengthband to display a specific (or set) color.

The non-display area NDA may be provided around the display area DPA.The non-display area NDA may entirely or partially surround the displayarea DPA. The display area DPA may be rectangular, and the non-displayarea NDA may be adjacent to four sides of the display area DPA. Thenon-display area NDA may form a bezel of the display device 10. In eachnon-display area NDA, wirings or circuit drivers included in the displaydevice 10 may be provided, and/or external devices may be mounted.

FIG. 2 is a schematic layout view of wirings included in the displaydevice 10 according to some embodiments.

Referring to FIG. 2, the display device 10 may include a plurality ofwirings. The wirings may include scan lines SCL, sensing lines SSL, datalines DTL, initialization voltage wirings VIL, a first voltage wiringVDL, and a second voltage wiring VSL. In some embodiments, other wiringsmay be further included in the display device 10.

The scan lines SCL and the sensing lines SSL may extend in the firstdirection DR1. The scan lines SCL and the sensing lines SSL may beconnected to a scan driver SDR. The scan driver SDR may include adriving circuit. The scan driver SDR may be on a side of the displayarea DPA in the first direction DR1, but the present disclosure is notlimited thereto. The scan driver SDR may be connected to a signal wiringpattern CWL, and at least one end of the signal wiring pattern CWL mayform a pad WPD_CW in the non-display area NDA to be connected to anexternal device.

In the present specification, the term “connect” may mean that any onemember and another member are connected (e.g., coupled) to each othereither through direct physical contact or through another member. Inaddition, it can be understood that any one portion (or member) andanother portion (or member) may be connected to each other as oneintegrated member. Further, when any one member and another member areconnected, it can be interpreted to include electrical connectionthrough another member and/or connection through direct contact.

The data lines DTL and the initialization voltage wirings VIL may extendin the second direction DR2 intersecting the first direction DR1. Thefirst voltage wiring VDL and the second voltage wiring VSL extend in thefirst direction DR1 and the second direction DR2. As will be describedhereinbelow, each of the first voltage wiring VDL and the second voltagewiring VSL may have a portion extending in the first direction DR1 and aportion extending in the second direction DR2, which are made ofconductive layers positioned on different layers (or levels), and mayhave a mesh structure in the entire display area DPA. However, thepresent disclosure is not limited thereto. Each pixel PX of the displaydevice 10 may be connected to at least one data line DTL, aninitialization voltage wiring VIL, the first voltage wiring VDL, and thesecond voltage wiring VSL.

Each of the data lines DTL, the initialization voltage wirings VIL, thefirst voltage wiring VDL and the second voltage wiring VSL may beelectrically connected to at least one wiring pad WPD. Each wiring padWPD may be provided in the non-display area NDA. In some embodiments,wiring pads WPD_DT (hereinafter, referred to as ‘data pads’) of the datalines DTL may be in a pad area PDA on one side of the display area DPAin the second direction DR2, and wiring pads WPD_Vint (hereinafter,referred to as ‘initialization voltage pads’) of the initializationvoltage wirings VIL, a wiring pad WPD_VDD (hereinafter, referred to as a‘first power pad’) of the first voltage wiring VDL and a wiring padWPD_VSS (hereinafter, referred to as a ‘second power pad’) of the secondvoltage wiring VSL may be in the pad area PDA located on the other sideof the display area DPA in the second direction DR2. In someembodiments, the data pads WPD_DT, the initialization voltage padsWPD_Vint, the first power pad WPD_VDD, and the second power pad WPD_VSSmay all be in the same area, for example, in the non-display area NDAlocated on an upper side of the display area DPA. An external device maybe mounted on the wiring pads WPD. For example, the external device maybe mounted on the wiring pads WPD through an anisotropic conductivefilm, ultrasonic bonding, and/or the like.

Each pixel PX or subpixel PXn (where n is an integer of 1 to 3) of thedisplay device 10 includes a pixel driving circuit. The above-describedwirings may transmit a driving signal to each pixel driving circuitwhile passing through and/or around each pixel PX. The pixel drivingcircuit may include a transistor and a capacitor. The number oftransistors and capacitors in each pixel driving circuit can bevariously suitably changed. According to some embodiments, each subpixelPXn of the display device 10 may have a 3T1C structure, in which thepixel driving circuit includes three transistors and one capacitor.Although the pixel driving circuit will be described below using the3T1C structure as an example, the present disclosure is not limitedthereto, and other various modified pixel structures (such as a 2T1Cstructure, a 7T1C structure, and/or a 6T1C structure) are alsoapplicable.

FIG. 3 is an equivalent circuit diagram of one subpixel PXn according tosome embodiments.

Referring to FIG. 3, each subpixel PXn of the display device 10according to some embodiments includes three transistors T1 through T3and one storage capacitor Cst, in addition to a light emitting diode EL.

The light emitting diode EL emits light according to a current suppliedthrough a first transistor T1. The light emitting diode EL includes afirst electrode, a second electrode, and at least one light emittingelement between them. The light emitting element may emit light of aspecific (or set) wavelength band in response to electrical signalsreceived from the first electrode and the second electrode.

A first end of the light emitting diode EL may be connected to a sourceelectrode of the first transistor T1, and a second end of the lightemitting diode EL may be connected to the second voltage wiring VSL towhich a low potential voltage (hereinafter, referred to as a secondpower supply voltage), lower than a high potential voltage (hereinafter,referred to as a first power supply voltage), is supplied. In addition,the second end of the light emitting diode EL may be connected to asource electrode of a second transistor T2.

The first transistor T1 adjusts a current flowing from the first voltagewiring VDL, to which the first power supply voltage is supplied, to thelight emitting diode EL according to a voltage difference between a gateelectrode and the source electrode. For example, the first transistor T1may be a driving transistor for driving the light emitting diode EL. Thefirst transistor T1 may have the gate electrode connected to the sourceelectrode of the second transistor T2, the source electrode connected tothe first electrode of the light emitting diode EL, and a drainelectrode connected to the first voltage wiring VDL to which the firstpower supply voltage is applied.

The second transistor T2 is turned on by a scan signal of a scan lineSCL to connect a data line DTL to the gate electrode of the firsttransistor T1. The second transistor T2 may have a gate electrodeconnected to the scan line SCL, the source electrode connected to thegate electrode of the first transistor T1, and a drain electrodeconnected to the data line DTL.

A third transistor T3 is turned on by a sensing signal of a sensing lineSSL to connect an initialization voltage wiring VIL to the first end ofthe light emitting diode EL. The third transistor T3 may have a gateelectrode connected to the sensing line SSL, a drain electrode connectedto the initialization voltage wiring VIL, and a source electrodeconnected to the first end of the light emitting diode EL or the sourceelectrode of the first transistor T1.

In some embodiments, the source electrode and the drain electrode ofeach of the transistors T1 through T3 are not limited to the abovedescription, and may be reversed. In addition, each of the transistorsT1 through T3 may be formed as a thin-film transistor. Although each ofthe transistors T1 through T3 is mainly described as an N-type metaloxide semiconductor field effect transistor (MOSFET) in FIG. 3, thepresent disclosure is not limited thereto. For example, each of thetransistors T1 through T3 may also be formed as a P-type MOSFET, or someof the transistors T1 through T3 may be formed as N-type MOSFETs, andthe other may be formed as a P-type MOSFET.

The storage capacitor Cst is formed between the gate electrode and thesource electrode of the first transistor T1. The storage capacitor Cststores a difference between a gate voltage and a source voltage of thefirst transistor T1.

The structure of one pixel PX of the display device 10 according to someembodiments will now be described in more detail by further referring toanother drawing.

FIG. 4 is a schematic plan view of wirings in one pixel PX of thedisplay device 10 according to some embodiments. In FIG. 4, schematicshapes of a plurality of wirings and a second bank BNL2 in each pixel PXof the display device 10 are illustrated. For ease of description, somemembers positioned in emission areas EMA1, EMA2 or EMA3 of each subpixelPXn and some conductive layers under the members are not illustrated. Ineach of the following drawings, both sides of the first direction DR1may be referred to as a left side and a right side, respectively, andboth sides of the second direction DR2 may be referred to as an upperside and a lower side, respectively. In FIG. 4, one pixel PX and aportion of another pixel PX adjacent to the one pixel PX in the firstdirection DR1 are illustrated together.

Referring to FIG. 4, each of the pixels PX of the display device 10 mayinclude a plurality of subpixels PXn (where n is an integer of 1 to 3).For example, one pixel PX may include a first subpixel PX1, a secondsubpixel PX2, and a third subpixel PX3.

One pixel PX of the display device 10 may include a plurality ofemission areas EMA1 through EMA3, and each subpixel PXn may include anemission area EMA1, EMA2 or EMA3 and a non-emission area. Each emissionarea EMA1, EMA2 or EMA3 may be an area in which light emitting elementsED (see FIG. 13) are provided to output light of a specific (or set)wavelength band, and the non-emission area may be an area in which thelight emitting elements ED are not provided and from which no light isoutput because light emitted from the light emitting elements ED doesnot reach this area. Each emission area EMA1, EMA2 or EMA3 may includean area where the light emitting elements ED are positioned and wherelight emitted from the light emitting elements ED is output to an areaadjacent to the light emitting elements ED.

However, the present disclosure is not limited thereto, and any of theemission area EMA1, EMA2 or EMA3 may also include an area from whichlight emitted from the light emitting elements ED is output after beingreflected or refracted by other members. A plurality of light emittingelements ED may be provided in each subpixel PXn, and an area where thelight emitting elements ED are provided, and an area adjacent to thisarea, may form the emission area EMA1, EMA2 or EMA3.

A first emission area EMA1 of the pixel PX is in the first subpixel PX1,a second emission area EMA2 is in the second subpixel PX2, and a thirdemission area EMA3 is in the third subpixel PX3. The subpixels PXninclude different types (or kinds) of light emitting elements ED so thatlights of different colors are emitted from the first through thirdemission areas EMA1 through EMA3. For example, the first subpixel PX1may emit light of a first color, the second subpixel PX2 may emit lightof a second color, and the third subpixel PX3 may emit light of a thirdcolor. The first color may be blue, the second color may be green, andthe third color may be red. However, the present disclosure is notlimited thereto, and the subpixels PXn may also include the same type(or kind) of light emitting elements ED so that light of the same coloris emitted from each of the emission areas EMA1 through EMA3 or onepixel PX.

In some embodiments, the pixel PX may include a plurality of cut areasCBA spaced apart from the emission areas EMA1 through EMA3. The cut areaCBA may be on a side of the emission area EMA1, EMA2 or EMA3 of eachsubpixel PXn in the second direction DR2, and may be between theemission areas EMA1, EMA2 or EMA3 of subpixels PXn neighboring eachother in the second direction DR2. The emission areas EMA1 through EMA3and the cut areas CBA may each be repeatedly arranged in the firstdirection DR1, but may be alternately arranged with each other in thesecond direction DR2. Light might not be output from the cut areas CBAbecause the light emitting elements ED are not provided in the cut areasCBA, but a portion of an electrode RME1 or RME2 (see FIG. 7) in eachsubpixel PXn may be positioned in the cut area CBA. Some of theelectrodes RME1 and RME2 in each subpixel PXn may be split in the cutarea CBA.

The second bank BNL2 may include portions extending in the firstdirection DR1 and the second direction DR2 in plan view to form alattice pattern over the entire display area DPA. The second bank BNL2may be at the boundary of each subpixel PXn, to separate neighboringsubpixels PXn. In some embodiments, the second bank BNL2 may surroundthe emission area EMA1, EMA2 or EMA3 and the cut area CBA in eachsubpixel PXn to separate them from each other. The second bank BNL2 willbe described in more detail hereinbelow.

The above-described wirings may be provided in each pixel PX of thedisplay device 10. For example, the display device 10 includes wiringhorizontal portions VDL_H and VSL_H of the first voltage wiring VDL andthe second voltage wiring VSL, in addition to the scan lines SCL and thesensing lines SSL extending in the first direction DR1. In addition, thedisplay device 10 includes the data lines DTL, the initializationvoltage wirings VIL, and wiring vertical portions VDL_V and VSL_V of thevoltage wirings VDL and VSL extending in the second direction DR2.

Wirings and circuit elements of a circuit layer provided in each pixelPX and connected to the light emitting diode EL may be connected to eachof the first through third subpixels PX1 through PX3. However, thewirings and the circuit elements are not placed to correspond to an areaoccupied by each subpixel PXn but may be positioned regardless (orirrespective) of the position of each subpixel PXn in one pixel PX. Forexample, in the display device 10 according to some embodiments, circuitlayers for driving the light emitting diode EL of each subpixel PXn maybe positioned regardless of the positions of the subpixels PXn in thepixels PX.

One pixel PX may include the first through third subpixels PX1 throughPX3, and a circuit layer connected to the pixel PX may be in a specificpattern. The patterns may be repeatedly arranged not on asubpixel-by-subpixel basis, but on a pixel-by-pixel basis. The subpixelsPXn in one pixel PX are areas distinguished by the emission areas EMA1through EMA3, and the circuit layer connected to the subpixels PXn maybe positioned regardless of (e.g., not corresponding to) the areas ofthe subpixels PXn. In the display device 10, because the wirings andelements of the circuit layer are placed repeatedly on a unitpixel-by-unit pixel basis (e.g., are patterned for each of the pixelsPX), the area occupied by the wirings and elements connected to eachsubpixel PXn can be minimized (or reduced), and a large number of pixelsPX and subpixels PXn can be included per unit area. Therefore, anultra-high resolution display device can be implemented.

A plurality of data lines DTL1 through DTL3 may extend in the seconddirection DR2 across a plurality of pixels PX arranged in the seconddirection DR2. In the display area DPA, the data lines DTL1 through DTL3may be in the pixels PX arranged in the second direction DR2 and may bespaced apart from each other in the first direction DR1. First throughthird data lines DTL1 through DTL3 may be in one pixel PX and may beconnected to each subpixel PXn, for example, the first through thirdsubpixels PX1 through PX3. The first data line DTL1, the second dataline DTL2, and the third data line DTL3 may be sequentially arrangedalong the first direction DR1. For example, while the first subpixelPX1, the subpixel PX2, and the third subpixel PX3 are sequentiallyarranged toward a first side (e.g., right side) of the first directionDR1, the first data line DTL1, the second data line DTL2, and the thirddata line DTL3 may be sequentially arranged toward a second side (e.g.,left side) of the first direction DR1. Each of the data lines DTL1through DTL3 may be connected to the second transistor T2 through aconductive pattern positioned in another conductive layer and maytransmit a data signal to the second transistor T2. However, asdescribed above, the first through third data lines DTL1 through DTL3might not be positioned to respectively correspond to areas occupied bythe first through third subpixels PX1 through PX3, but instead may beplaced at one or more specific (or set) positions in one pixel PX.Although the first through third data lines DTL1 through DTL3 arearranged across the first subpixel PX1 and the second subpixel PX2 inthe drawing (e.g., in FIG. 4), the present disclosure is not limitedthereto.

The initialization voltage wirings VIL extend in the second directionDR2 across the pixels PX arranged in the second direction DR2. In thedisplay area DPA, the initialization voltage wirings VIL may be spacedapart from each other in the first direction DR1, and each of theinitialization voltage wirings VIL may be arranged across a plurality ofpixels PX arranged in the same column (along the second direction DR2).An initialization voltage wiring VIL may be positioned on a left side ofthe first data line DTL1 in plan view. One initialization voltage wiringVIL may be provided per one pixel PX in the first direction DR1 and maybe connected to each subpixel PXn by being connected to a conductivepattern in another conductive layer. Each initialization voltage wiringVIL may be electrically connected to the drain electrode of the thirdtransistor T3 and may apply an initialization voltage to the thirdtransistor T3.

The first voltage wiring VDL and the second voltage wiring VSL mayextend in the first direction DR1 and the second direction DR2. In someembodiments, the first voltage wiring VDL and the second voltage wiringVSL may respectively include the wiring vertical portions VDL_V andVSL_V extending in the second direction DR2. The wiring verticalportions VDL_V and VSL_V extend in the second direction DR2 across aplurality of pixels PX neighboring in the second direction DR2. A firstwiring vertical portion VDL_V of the first voltage wiring VDL may be ona right side of a center of each pixel PX, which is the first side ofthe first direction DR1, and a second wiring vertical portion VSL_V ofthe second voltage wiring VSL may be on a left side, which is the secondside of the first direction DR1. Each of the wiring vertical portionsVDL_V and VSL_V may intersect the wiring horizontal portion VDL_H orVSL_H to be described hereinbelow, and may be connected to the wiringhorizontal portion VDL_H or VSL_H through a contact hole at theintersection with the wiring horizontal portion VDL_H or VSL_H to formone voltage wiring VDL or VSL.

The data lines DTL1 through DTL3, the initialization voltage wiringsVIL, and the wiring vertical portions VDL_V and VSL_V of the voltagewirings VDL and VSL may each be made of a first conductive layer. Thefirst conductive layer may include another conductive layer in additionto the above-described wirings and lines.

The scan lines SCL and the sensing lines SSL may extend in the firstdirection DR1 across a plurality of pixels PX arranged in the firstdirection DR1. For example, the scan lines SCL and the sensing lines SSLmay be spaced apart from each other in the second direction DR2, andeach of the scan lines SCL and each of the sensing lines SSL may beprovided across a plurality of pixels PX arranged in the same row in thefirst direction DR1. A scan line SCL may be on a lower side of thecenter of each pixel PX in plan view, and a sensing line SSL may be onan upper side of the center of each pixel PX in plan view. The scan lineSCL and the sensing line SSL may be in the non-emission area locatedoutside the emission areas EMA1 through EMA3, but a portion of thesensing line SSL may also be positioned across the emission areas EMA1through EMA3. In some embodiments, the scan line SCL and the sensingline SSL may be connected to a gate pattern, which is in a secondconductive layer provided on the first conductive layer and whichextends in the second direction DR2, and the gate pattern may form thegate electrode of the second transistor T2 or the third transistor T3.

The wiring horizontal portions VDL_H and VSL_H of the first voltagewiring VDL and the second voltage wiring VSL may extend in the firstdirection DR1 across a plurality of pixels PX neighboring in the firstdirection DR1. The wiring horizontal portions VDL_H and VSL_H may bespaced apart from each other in the second direction DR2, and each ofthe wiring horizontal portions VDL_H and VSL_H may be provided across aplurality of pixels PX arranged in the same row in the first directionDR1. A first wiring horizontal portion VDL_H of the first voltage wiringVDL may be on the lower side of the center of each pixel PX, which is asecond side of the second direction DR2, and a second wiring horizontalportion VSL_H of the second voltage wiring VSL may be on the upper side,which is a first side of the second direction DR2. The wiring verticalportions VDL_V and VSL_V and the wiring horizontal portions VDL_H andVSL_H may be made of conductive layers provided on different layers(different levels) and may be connected to each other through contactholes. For example, the first wiring horizontal portion VDL_H may be onthe lower side of the pixel PX and may be connected to the first wiringvertical portion VDL_V through a contact hole at an intersection withthe first wiring vertical portion VDL_V, but might not be connected tothe second wiring vertical portion VSL_V at an intersection with thesecond wiring vertical portion VSL_V. Similarly, the second wiringhorizontal portion VSL_H may be on the upper side of the pixel PX andmay be connected to the second wiring vertical portion VSL_V through acontact hole at an intersection with the second wiring vertical portionVSL_V, but might not be connected to the first wiring vertical portionVDL_V at an intersection with the first wiring vertical portion VDL_V.

In some embodiments, the first voltage wiring VDL and the second voltagewiring VSL may be outside the emission areas EMA1 through EMA3 of eachpixel PX to extend in the first direction DR1 and the second directionDR2. The first voltage wiring VDL and the second voltage wiring VSL maybe in a mesh structure in the entire display area DPA, to surround theemission areas EMA1 through EMA3, and may be electrically connected toelectrode lines RM1 and RM2 positioned outside the emission areas EMA1through EMA3.

In some embodiments, the first through third subpixels PX1 through PX3of each pixel PX may share the same first voltage wiring VDL and secondvoltage wiring VSL. As described above, a plurality of subpixels PXn ineach pixel PX may share the first voltage wiring VDL and the secondvoltage wiring VSL to which the same signal is transmitted. Therefore,the number of wirings per unit area can be reduced.

The first voltage wiring VDL may be electrically connected to the drainelectrode of the first transistor T1 of each subpixel PXn and may applythe first power supply voltage to the first transistor T1. The secondvoltage wiring VSL may be electrically connected to the second electrodeof the light emitting diode EL and may apply the second power supplyvoltage to the light emitting element.

Although one each of the wiring vertical portions VDL_V and VSL_V andthe wiring horizontal portions VDL_H and VSL_H is in one pixel PX in thedrawing (e.g., in FIG. 4), the present disclosure is not limitedthereto. The respective wiring vertical portions VDL_V and VSL_V andwiring horizontal portions VDL_H and VSL_H of the first voltage wiringVDL and the second voltage wiring VSL may be placed to correspond to onepixel PX, and may also be shared with pixels PX adjacent to the onepixel PX in the first direction DR1 and the second direction DR2. Inthis case, the wiring vertical portions VDL_V and VSL_V need not berepeatedly arranged along the first direction DR1 on a pixel-by-pixelbasis (e.g., might not be repeatedly arranged to be included in everypixel PX along the first direction DR1), but may be alternately arranged(e.g., may be arranged in every other pixel PX, or every third or more,along the first direction DR1), and the wiring horizontal portions VDL_Hand VSL_H need not be repeatedly arranged along the second direction DR2(e.g., might not be repeatedly arranged to be included in every pixel PXalong the second direction DR2), but may be alternately arranged (e.g.,may be arranged in every other pixel PX, or every third or more, alongthe second direction DR2). Accordingly, in some of the pixels PX, thewirings and elements of a circuit layer connected to the light emittingdiodes EL may be positioned symmetrically to each other with respect toa boundary between respective ones of the pixels PX (which are notnecessarily directly adjacent one another). In some embodiments, thelight emitting elements ED, electrodes RME1 and RME2, and the electrodelines RM1 and RM2 to be described hereinbelow may have a specific (orset) direction, and the light emitting elements ED and the electrodesRME1 and RME2 may be positioned symmetrically to each other in thepixels PX. This will be described in more detail hereinbelow.

The scan lines SCL, the sensing lines SSL, and the wiring horizontalportions VDL_H and VSL_H may be made of a third conductive layerprovided on the second conductive layer. The third conductive layer mayinclude other conductive patterns, in addition to the above wirings andlines.

In the display device 10 according to some embodiments, a circuit layerthat transmits a signal for driving the light emitting diode EL mayinclude the first through third conductive layers. For example, each ofthe first voltage wiring VDL and the second voltage wiring VSL, whichapply power supply voltages to the light emitting diode EL, may becomposed of wirings in the first conductive layer and the thirdconductive layer and may be positioned on the same layer (e.g., samelevel) as the data lines DTL, the initialization voltage wirings VIL,and/or other conductive patterns. Because the display device 10 canreduce the number of conductive layers constituting the circuit layer,it is advantageous in terms of a manufacturing process. The structure ofeach subpixel PXn will now be described in more detail by furtherreferring to other drawings.

FIG. 5 is a layout view of a plurality of conductive layers included inone pixel PX of the display device 10 according to some embodiments.FIG. 6 is a layout view illustrating the arrangement of the firstconductive layer, the second conductive layer, and a semiconductor layerincluded in one pixel PX of the display device 10 according to someembodiments. FIG. 7 is a schematic plan view of a plurality ofelectrodes and a plurality of banks included in one pixel PX of thedisplay device 10 according to some embodiments. FIG. 8 is across-sectional view taken along lines Q1-Q1′, Q2-Q2′ and Q3-Q3′ of FIG.7. FIG. 9 is a cross-sectional view taken along lines Q4-Q4′, Q5-Q5′ andQ6-Q6′ of FIG. 7.

In FIG. 5, the planar arrangement of wirings and elements of a circuitlayer connected to one pixel PX is illustrated. In FIG. 6, the planararrangement of the first conductive layer, the second conductive layerand an active layer of the circuit layer of FIG. 5 is illustrated. InFIGS. 5 and 6, the conductive layers of the circuit layer in one pixelPX are illustrated, and some of the elements of a circuit layer inanother pixel PX neighboring to the one pixel PX in the first directionDR1 are also illustrated.

FIG. 7 illustrates a display element layer in each pixel PX, based oneach subpixel PXn defined by the second bank BNL2. FIG. 7 illustratesthe arrangement of a plurality of electrode lines RM1 and RM2, aplurality of banks BNL1 and BNL2, and contact electrodes CNE1 and CNE2,in addition to the electrodes RME1 and RME2 and the light emittingelements ED constituting each light emitting diode EL. FIGS. 8 and 9illustrate cross-sections of a first transistor T1, a second transistorT2, and a third transistor T3.

Referring to FIGS. 5 through 9 in connection with FIG. 4, the displaydevice 10 may include the circuit layer and the display element layer.The display element layer may be a layer in which the electrode linesRM1 and RM2 and first and second electrodes RME1 and RME2, as well asthe light emitting elements ED of each light emitting diode EL, areprovided, and the circuit layer may be a layer in which a plurality ofwirings, as well as pixel circuit elements for driving each lightemitting diode EL, are provided. For example, the circuit layer mayinclude the transistors T1 through T3, in addition to a scan line SCL, asensing line SSL, data lines DTL, an initialization voltage line VIL,the first voltage wiring VDL, and the second voltage wiring VSL.

In some embodiments, the display device 10 includes a first substrateSUB on which the circuit layer and the display element layer arepositioned. The first substrate SUB may be an insulating substrate andmay be made of an insulating material such as glass, quartz, and/orpolymer resin. In some embodiments, the first substrate SUB may be arigid substrate, but may also be a flexible substrate that can be bent,folded, and/or rolled.

The first conductive layer may be on the first substrate SUB. The firstconductive layer includes the wiring vertical portions VDL_V and VSL_Vof the voltage wirings VDL and VSL, the initialization voltage wringVIL, the data lines DTL1 through DTL3, and a plurality of light blockinglayers BML1 through BML3.

The wiring vertical portions VDL_V and VSL_V of the voltage wirings VDLand VSL extend in the second direction DR2. The wiring vertical portionsVDL_V and VSL_V of the voltage wirings VDL and VSL are in thenon-emission area at positions overlapping the second bank BNL2 in thethird direction DR3, which is a thickness direction, so as not tooverlap the emission areas EMA1 through EMA3. They may be connected tothe pads WPD_VDD and WPD_VSS of the pad area PDA and may receive thefirst power supply voltage and the second power supply voltage.

The first wiring vertical portion VDL_V of the first voltage wiring VDLmay be connected to the drain electrodes of the first transistors T1through a first conductive pattern DP1 of the third conductive layer. Insome embodiments, the first wiring vertical portion VDL_V may beconnected to the first wiring horizontal portion VDL_H through a firstwiring contact hole CTV1 at an intersection with the first wiringhorizontal portion VDL_H. The second wiring vertical portion VSL_V ofthe second voltage wiring VSL may be connected to the second electrodesRME2 through a fifth conductive pattern DP5 of the third conductivelayer. The second wiring vertical portion VSL_V may be connected to thesecond wiring horizontal portion VSL_H through a second wiring contacthole CTV2 at an intersection with the second wiring horizontal portionVSL_H.

The initialization voltage wiring VIL may extend in the second directionDR2 and may be between the wiring vertical portions VDL_V and VSL_V. Theinitialization voltage wiring VIL may be connected to the drainelectrodes of the third transistors T3 through a fourth conductivepattern DP4 of the third conductive layer and may deliver theinitialization voltage to the third transistor T3 of each subpixel PXn.

The light blocking layers BML1 through BML3 may be on the firstsubstrate SUB. The light blocking layers BML1 through BML3 overlap firstactive layers ACT1 of the semiconductor layer and first capacitiveelectrodes CSE1 of the second conductive layer, which will be describedin more detail hereinbelow. A first light blocking layer BML1 overlapsthe first active layer ACT1 of a first transistor T1_1 connected to thefirst subpixel PX1. A second light blocking layer BML2 overlaps thefirst active layer ACT1 of a first transistor T1_2 connected to thesecond subpixel PX2, and a third light blocking layer BML3 overlaps thefirst active layer ACT1 of a first transistor T1_3 connected to thethird subpixel PX3. The first through third light blocking layers BML1through BML3 are spaced apart from each other in the second directionDR2 and may be on a right side of and adjacent to the center of eachpixel PX in plan view. The light blocking layers BML1 through BML3include a light blocking material and prevent (or reduce) light fromentering the first active layers ACT1 of the first transistors T1. Forexample, the light blocking layers BML1 through BML3 may be made of anopaque metal material that blocks (or substantially reduces)transmission of light. However, the present disclosure is not limitedthereto. In some embodiments, the light blocking layers BML1 throughBML3 may be omitted or may overlap active layers of other transistors T1through T3.

The data lines DTL1 through DTL3 extend in the second direction DR2between the initialization voltage wiring VIL and the light blockinglayers BML1 through BML3. The data lines DTL1 through DTL3 may beconnected to third conductive patterns DP3 of the third conductive layerand connected to the drain electrodes of the second transistors T2through the third conductive patterns DP3. The first data line DTL1 maybe connected to a second transistor T2_1 of the first subpixel PX1, thesecond data line DTL2 may be connected to a second transistor T2_2 ofthe second subpixel PX2, and the third data line DTL3 may be connectedto a second transistor T2_3 of the third subpixel PX3.

A buffer layer BF may be entirely on the first substrate SUB having thefirst conductive layer. The buffer layer BF may be formed on the firstsubstrate SUB to protect the transistors T1 through T3 from moistureintroduced through the first substrate SUB, which may be vulnerable tomoisture penetration, and may perform a surface planarization function.

The semiconductor layer may be on the buffer layer BF. The semiconductorlayer may include the respective active layers ACT1 through ACT3 of thetransistors T1 through T3.

One pixel PX may include a plurality of first active layers ACT1included in the first transistors T1_1 through T1_3 connected to thesubpixels PX1 through PX3, respectively. The first active layer ACT1 ofeach first transistor T1 may be adjacent to and on the right side of thecenter of each pixel PX. A first drain region D1 is formed on a side ofthe first active layer ACT1, and a first source region S1 is formed onthe other side of the first active layer ACT1. The first active layersACT1 may be spaced apart from each other in the second direction DR2,and the first drain regions D1 and the first source regions S1 mayoverlap the first wiring vertical portion VDL_V and the light blockinglayers BML1 through BML3. The first drain regions D1 may be on the firstwiring vertical portion VDL_V, and the first source regions S1 mayoverlap second capacitive electrodes CSE2 of the third conductive layer.The first drain regions D1 of the first transistors T1 may be connectedto the first voltage wiring VDL through the first conductive patternDP1, and the first source regions S1 may be connected to the secondcapacitive electrodes CSE2.

One pixel PX may include a plurality of second active layers ACT2included in the second transistors T2_1 through T2_3 connected to thesubpixels PX1 through PX3, respectively. The second active layer ACT2 ofeach second transistor T2 may be adjacent to and on a left side of thecenter of each pixel PX. A second drain region D2 is formed on a side ofthe second active layer ACT2, and a second source region S2 is formed onthe other side of the second active layer ACT2. The second active layersACT2 may be spaced apart from each other in the second direction DR2,and the second drain regions D2 and the second source regions S2 mayoverlap the data lines DTL1 through DTL3 and the third conductivepatterns DP3 and second conductive patterns DP2 of the third conductivelayer. The second drain regions D2 may be connected to the thirdconductive patterns DP3, and thus connected to the data lines DTLthrough the third conductive patterns DP3, and the second source regionsS2 may be connected to the second conductive patterns DP2, and thusconnected to the gate electrodes of the first transistors T1 through thesecond conductive patterns DP2.

The second active layers ACT2 of the second transistors T2 may havedifferent widths measured in the first direction DR1. The second sourceregions S2 formed on one side of the second active layers ACT2 mayoverlap the second conductive patterns DP2 arranged in the seconddirection DR2, and the second drain regions D2 formed on the other sideof the second active layers ACT2 may overlap different data lines DTL1through DTL3 arranged in the first direction DR1. The first data lineDTL1 may be closest to the second source regions S2 of the secondtransistors T2, and the third data line DTL3 may be farthest from thesecond source regions S2 of the second transistors T2. Accordingly, thesecond active layer ACT2 of the second transistor T2_1 connected to thefirst subpixel PX1 may be shorter than the second active layer ACT2 ofthe second transistor T2_2 connected to the second subpixel PX2 and thesecond active layer ACT2 of the second transistor T2_3 connected to thethird subpixel PX3. In addition, the second active layer ACT2 of thesecond transistor T2_2 connected to the second subpixel PX2 may beshorter than the second active layer ACT2 of the second transistor T2_3connected to the third subpixel PX3. However, the present disclosure isnot limited thereto.

One pixel PX may include a plurality of third active layers ACT3included in third transistors T3_1 through T3_3 connected to thesubpixels PX1 through PX3, respectively. The third active layer ACT3 ofeach third transistor T3 may be on the right side of each pixel PX toextend to another pixel PX adjacent in the first direction DR1. A thirddrain region D3 is formed on a side of the third active layer ACT3, anda third source region S3 is formed on the other side of the third activelayer ACT3. The third active layers ACT3 may be spaced apart from eachother in the second direction DR2, and the third drain regions D3 andthe third source regions S3 may overlap the initialization voltagewiring VIL and the second capacitive electrodes CSE2 of the thirdconductive layer located in different pixels PX. The third drain regionsD3 may be connected to the fourth conductive pattern DP4 and thusconnected to the initialization voltage wiring VIL through the fourthconductive pattern DP4, and the third source regions S3 may be connectedto the second capacitive electrodes CSE2.

In some embodiments, the semiconductor layer may include polycrystallinesilicon, monocrystalline silicon, an oxide semiconductor, and/or thelike. The polycrystalline silicon may be formed by crystallizingamorphous silicon. When the semiconductor layer includes an oxidesemiconductor, each of the active layers ACT1 through ACT3 may include aplurality of conducting regions and a channel region between them. Theoxide semiconductor may be an oxide semiconductor containing indium(In). In some embodiments, the oxide semiconductor may be indium tinoxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indiumzinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium galliumtin oxide (IGTO), and/or indium gallium zinc tin oxide (IGZTO).

In some embodiments, the semiconductor layer may include polycrystallinesilicon. The polycrystalline silicon may be formed by crystallizingamorphous silicon. In this case, each of the conducting regions of theactive layers ACT1 though ACT3 may be, but is not limited to, a dopingregion doped with impurities.

A first gate insulating layer GI is on the semiconductor layer and thebuffer layer BF. The first gate insulating layer GI may be on the bufferlayer BF having the semiconductor layer. The first gate insulating layerGI may function as a gate insulating film of each transistor.

The second conductive layer is on the first gate insulating layer GI.The second conductive layer may include the first capacitive electrodesCSE1 of storage capacitors, a first gate pattern DP_C, a second gatepattern DP_S, and a third gate pattern DP_R constituting respective gateelectrodes G1 through G3 of the transistors T1 through T3.

A plurality of first capacitive electrodes CSE1 may be provided in onepixel PX. Each of the first capacitive electrodes CSE1 may overlap thefirst active layer ACT1 of the first transistor T1, and a portionoverlapping the first active layer ACT1 may form a first gate electrodeG1 of the first transistor T1. In some embodiments, the first capacitiveelectrodes CSE1 may overlap the light blocking layers BML1 through BML3and the second capacitive electrodes CSE2 of the third conductive layer.The first capacitive electrodes CSE1 may be electrically connected tothe source electrodes of the second transistors T2. For example, thefirst capacitive electrodes CSE1 may be integrated with the first gateelectrodes G1 and may be connected to the second conductive patternsDP2, which are connected to the second source regions S2 of the secondtransistors T2, through contact holes.

The first gate pattern DP_C may include a portion extending in the firstdirection DR1 and a portion connected to the above portion and extendingin the second direction DR2. The portion of the first gate pattern DP_Cextending in the first direction DR1 may be on the lower side of eachpixel PX to overlap the scan line SCL. The first gate pattern DP_C mayoverlap the second active layers ACT2 and may form second gateelectrodes G2 of the second transistors T2. The first gate pattern DP_Cmay be electrically connected to the scan line SCL, and a scan signalmay be transmitted to the second transistors T2.

The second gate pattern DP_S may extend in the second direction DR2. Thesecond gate pattern DP_S may be on an upper left side of each pixel PXto overlap the sensing line SSL. In the drawings, the second gatepattern DP_S is in each of one pixel PX and another adjacent pixel PXneighboring the pixel PX. The second gate pattern DP_S may overlap thethird active layers ACT3 and may form third gate electrodes G3 of thethird transistors T3. The second gate pattern DP_S may be electricallyconnected to the sensing line SSL, and a sensing signal may betransmitted to the third transistors T3.

The third gate pattern DP_R may be above the first capacitive electrodesCSE1 to overlap the sensing line SSL. The third gate pattern DP_R may beconnected to the sensing line SSL to lower (e.g., reduce) wiringresistance of the sensing line SSL extending in the first direction DR1.

A first interlayer insulating layer IL1 is on the second conductivelayer. The first interlayer insulating layer IL1 may cover the secondconductive layer to protect the second conductive layer.

The third conductive layer is on the first interlayer insulating layerIL1. The third conductive layer includes the scan line SCL, the sensingline SSL, the wiring horizontal portions VDL_H and VSL_H, and the secondcapacitive electrodes CSE2. In some embodiments, the third conductivelayer may include a plurality of conductive patterns DP1 through DP5connected to the source regions S1 through S3 and the drain regions D1through D3 of the transistors T1 through T3, or connected to the wiringvertical portions VDL_V and VSL_V, or the initialization voltage wiringVIL.

The scan line SCL and the sensing line SSL extend in the first directionDR1 and are on the upper and lower sides of each pixel PX. The scan lineSCL may be on the lower side of each pixel PX to overlap the first gatepattern DP_C and may be connected to the first gate pattern DP_C throughtenth contact holes CT10 penetrating the first interlayer insulatinglayer IL1. The sensing line SSL may be on the upper side of each pixelPX to overlap the second gate pattern DP_S and the third gate patternDP_R and may be connected to the second gate pattern DP_S and the thirdgate pattern DP_R through an eleventh contact hole CT11 and twelfthcontact holes CT12, respectively, penetrating the first interlayerinsulating layer IL1.

A plurality of second capacitive electrodes CSE2 are in one pixel PX.The second capacitive electrodes CSE2 may overlap the first capacitiveelectrodes CSE1, the first source regions S1 of the first transistorsT1, and the third source regions S3 of the third transistors T3,respectively. The second capacitive electrodes CSE2 may overlap thefirst capacitive electrodes CSE1 in the thickness direction, with thefirst interlayer insulating layer IL1 interposed between them, and thestorage capacitors Cst may be formed between them. In some embodiments,a portion of each second capacitive electrode CSE2 may be connected tothe first source region S1 of a first transistor T1 through a firstcontact hole CT1 penetrating the first gate insulating layer GI and thefirst interlayer insulating layer IL1, and may form the source electrodeof the first transistor T1. The second capacitive electrodes CSE2 may beconnected to the light blocking layers BML1 through BML3 through fourthcontact holes CT4 penetrating the buffer layer BF, the first gateinsulating layer GI and the first interlayer insulating layer IL1, andthe source electrodes of the first transistors T1 may be connected tothe light blocking layers BML1 through BML3. Another portion of eachsecond capacitive electrode CSE2 may be connected to the third sourceregion S3 of a third transistor T3 through a third contact hole CT3penetrating the first gate insulating layer GI and the first interlayerinsulating layer IL1, and may form the source electrode of the thirdtransistor T3.

In some embodiments, the second capacitive electrodes CSE2 may beconnected to the first electrodes RME1 and may transmit electricalsignals received through the first transistors T1 to the firstelectrodes RME1. Of the second capacitive electrodes CSE2, a secondcapacitive electrode CSE2 connected to the first subpixel PX1 mayfurther include an extension electrode portion EP extending in the firstdirection DR1, and the extension electrode portion EP may directlycontact the first electrode RME1. Second capacitive electrodes CSE2connected to the second subpixel PX2 and the third subpixel PX3 may beconnected to the first electrodes RME1 in portions overlapping the firstcapacitive electrodes CSE1 without including the extension electrodeportion EP.

The first conductive pattern DP1 may be on the right side of each pixelPX to extend in the second direction DR2. The first conductive patternDP1 may overlap the first wiring vertical portion VDL_V in the thicknessdirection and may be connected to the first wiring vertical portionVDL_V through sixth contact holes CT6 penetrating the buffer layer BF,the first gate insulating layer GI and the first interlayer insulatinglayer IL1. In some embodiments, the first conductive pattern DP1 may beconnected to the first drain region D1 of each first transistor T1through the first contact hole CT1 penetrating the first gate insulatinglayer GI and the first interlayer insulating layer IL1, and may form thedrain electrode of each first transistor T1. The first transistors T1may be connected to the first voltage wiring VDL through the firstconductive pattern DP1 and may receive the first power supply voltage.

The second conductive patterns DP2 may be at the center of each pixel PXand may overlap the first capacitive electrodes CSE1 and the secondsource regions S2 of the second transistors T2 in the thicknessdirection (e.g., in the third direction DR3). Each of the secondconductive patterns DP2 may contact the second source region S2 througha second contact hole CT2 penetrating the first gate insulating layer GIand the first interlayer insulating layer IL1. Each of the secondconductive patterns DP2 may form the source electrode of a secondtransistor T2. In some embodiments, the second conductive patterns DP2may be connected to the first capacitive electrodes CSE1 through fifthcontact holes CT5 penetrating the first interlayer insulating layer IL1and may be connected to the first gate electrodes G1 of the firsttransistors T1.

The third conductive patterns DP3 may be at the center of each pixel PXto overlap the data lines DTL1 through DTL3 and the second drain regionsD2 of the second transistors T2 in the thickness direction. The thirdconductive patterns DP3 may overlap the second drain regions D2 of thesecond transistors T2_1 through T2_3 respectively connected to thesubpixels PX1 through PX3, and the data lines DTL1 through DTL3,respectively. The third conductive patterns DP3 may contact the seconddrain regions D2 through the second contact holes CT2 penetrating thefirst gate insulating layer GI and the first interlayer insulating layerIL1. In some embodiments, the third conductive patterns DP3 may beconnected to the data lines DTL1 through DTL3 through seventh contactholes CT7 penetrating the buffer layer BF, the first gate insulatinglayer GI and the first interlayer insulating layer IL1. Different thirdconductive patterns DP3 may form the drain electrodes of the secondtransistors T2, and the second transistors T2 may be connected to thedata lines DTL1 through DTL3 through the third conductive patterns DP3.

The fourth conductive pattern DP4 may be on the left side of each pixelPX to extend in the second direction DR2. The fourth conductive patternDP4 may overlap the initialization voltage wiring VIL in the thicknessdirection and may be connected to the initialization voltage wiring VILthrough eighth contact holes CT8 penetrating the buffer layer BF, thefirst gate insulating layer GI and the first interlayer insulating layerIL1. In some embodiments, the fourth conductive pattern DP4 may beconnected to the third drain region D3 of each third transistor T3through the third contact hole CT3 penetrating the first gate insulatinglayer GI and the first interlayer insulating layer IL1, and may form thedrain electrode of each third transistor T3. The third transistors T3may be connected to the initialization voltage wiring VIL through thefourth conductive pattern DP4 and may receive the initializationvoltage.

The fifth conductive pattern DP5 may be on the left side of each pixelPX to extend in the second direction DR2. The fifth conductive patternDP5 may overlap the second wiring vertical portion VSL_V in thethickness direction and may be connected to the second wiring verticalportion VSL_V through ninth contact holes CT9 penetrating the bufferlayer BF, the first gate insulating layer GI and the first interlayerinsulating layer IL1. In some embodiments, the fifth conductive patternDP5 may be connected to a second electrode line RM2 to be describedhereinbelow in more detail, and may apply the second power supplyvoltage to the second electrode line RM2 and the second electrodes RME2.

The wiring horizontal portions VDL_H and VSL_H of the voltage wiringsVDL and VSL may be on the lower and upper sides of each pixel PX,respectively. The first wiring horizontal portion VDL_H may be connectedto the first wiring vertical portion VDL_V through the first wiringcontact hole CTV1, which penetrates the buffer layer BF, the first gateinsulating layer GI and the first interlayer insulating layer IL1, atthe intersection with the first wiring vertical portion VDL_V.Similarly, the second wiring horizontal portion VSL_H may be connectedto the second wiring vertical portion VSL_V through the second wiringcontact hole CTV2, which penetrates the buffer layer BF, the first gateinsulating layer GI and the first interlayer insulating layer IL1, atthe intersection with the second wiring vertical portion VSL_V.

A second interlayer insulating layer IL2 may be on the third conductivelayer. The second interlayer insulating layer IL2 may function as aninsulating film between the third conductive layer and other layers onthe third conductive layer. In some embodiments, the second interlayerinsulating layer IL2 may cover the third conductive layer and protectthe third conductive layer. In some embodiments, the second interlayerinsulating layer IL2 may perform a surface planarization function.

Each of the first through third conductive layers described above maybe, but is not limited to, a single layer or a multilayer made of anyone or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr),gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), andalloys of the same.

In some embodiments, each of the buffer layer BF, the first gateinsulating layer GI, the first interlayer insulating layer IL1 and thesecond interlayer insulating layer IL2 described above may be aninorganic layer including an inorganic material such as silicon oxide(SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiOxNy), ormay have a structure in which the above materials are stacked.

A plurality of first banks BNL1, the electrode lines RM1 and RM2, theelectrodes RME1 and RME2, the light emitting element ED, the second bankBNL2 and the contact electrodes CNE1 and CNE2 may be on the secondinterlayer insulating layer IL2. In some embodiments, a plurality ofinsulating layers PAS1 and PAS2 may be further provided on the secondinterlayer insulating layer IL2.

The first banks BNL1 may be directly on the second interlayer insulatinglayer IL2. One subpixel PXn includes a plurality of first banks BNL1 inthe emission area EMA1, EMA2 or EMA3 and spaced apart from each other.For example, in one subpixel PXn, two first banks BNL1 may be in theemission area EMA1, EMA2 or EMA3, and may be spaced apart from eachother in the first direction DR1. The light emitting element ED may bebetween the first banks BNL1 spaced apart in the first direction DR1.Although two first banks BNL1 are illustrated in the drawings as beingin the emission area EMA1, EMA2 or EMA3 of each subpixel PXn to formlinear or stripe patterns, the present disclosure is not limitedthereto. The number of the first banks BNL1 in the emission area EMA1,EMA2 or EMA3 of each subpixel PXn may vary according to the number ofthe electrodes RME1 and RME2, and/or the arrangement of the lightemitting elements ED.

Lengths of the first banks BNL1 measured in the second direction DR2 maybe smaller than lengths of the emission areas EMA1 through EMA3 measuredin the second direction DR2. Therefore, each first bank BNL1 might notoverlap the second bank BNL2 of the non-emission area.

At least a portion of each first bank BNL1 may protrude from an uppersurface of the second interlayer insulating layer IL2. The protrudingportion of each first bank BNL1 may have inclined side surfaces, andlight emitted from the light emitting elements ED may be reflected bythe electrodes RME1 and RME2 on the first banks BNL1 to travel towardabove the second interlayer insulating layer IL2. The first banks BNL1may provide an area where the light emitting elements ED are positioned,while functioning as reflective barriers that can reflect light emittedfrom the light emitting elements ED in an upward direction (here, upwarddirection may refer to DR3 direction, or thickness direction). The sidesurfaces of the first banks BNL1 may be inclined in a linear shape(e.g., may be inclined lines). However, the present disclosure is notlimited thereto, and outer surfaces of the first banks BNL1 may have acurved semi-circular and/or semi-elliptical shape. The first banks BNL1may include an organic insulating material such as polyimide (PI), butthe present disclosure is not limited thereto.

The electrodes RME1 and RME2 extend in a direction and are provided ineach subpixel PXn. For example, the electrodes RME1 and RME2 may extendin the second direction DR2, may be spaced apart from each other in thefirst direction DR1, and may be provided in each subpixel PXn. Theelectrodes RME1 and RME2 may include the first electrode RME1 and thesecond electrode RME2, and a plurality of light emitting elements ED maybe provided on the first and second electrodes RME1 and RME2. Althoughone first electrode RME1 and one second electrode RME2 in each subpixelPXn are illustrated in the drawings, the present disclosure is notlimited thereto. The arrangement of the electrodes RME1 and RME2 in eachsubpixel PXn may vary according to the number of the electrodes RME1 andRME2, and/or the number of the light emitting elements ED in eachsubpixel PXn.

The electrodes RME1 and RME2 in each subpixel PXn may be respectivelypositioned on the first banks BNL1 spaced apart from each other. Each ofthe electrodes RME1 and RME2 may be on a side of a first bank BNL1 inthe first direction DR1 and may be on an inclined side surface of thefirst bank BNL1. In some embodiments, widths of the electrodes RME1 andRME2 measured in the first direction DR1 may be smaller than widths ofthe first banks BNL1 measured in the first direction DR1. Each of theelectrodes RME1 and RME2 may cover at least one side surface of thefirst bank BNL1 to reflect light emitted from the light emittingelements ED.

In some embodiments, a gap between the electrodes RME1 and RME2 in thefirst direction DR1 may be smaller than a gap between the first banksBNL1. At least a portion of each of the electrodes RME1 and RME2 may bedirectly on the second interlayer insulating layer IL2, and thus theportions may lie in the same plane.

The display device 10 according to some embodiments may include theelectrode lines RM1 and RM2 outside the emission areas EMA1 through EMA3of each pixel PX to surround the emission areas EMA1 through EMA3. Theelectrode lines RM1 and RM2 may include a first electrode line RM1extending in the second direction DR2 on the right side of each pixel PXand overlapping the first wiring vertical portion VDL_V of the firstvoltage wiring VDL and the second electrode line RM2 extending in thesecond direction DR2 on the left side of each pixel PX and overlappingthe second wiring vertical portion VSL_V of the second voltage wiringVSL. Each of the electrode lines RM1 and RM2 may partially overlap thefirst voltage wiring VDL or the second voltage wiring VSL and may beconnected to the first voltage wiring VDL or the second voltage wiringVSL.

In some embodiments, each of the first electrode line RM1 and the secondelectrode line RM2 may further include a portion branching in the firstdirection DR1. For example, the first electrode line RM1 may include afirst electrode stem portion RM1_S extending in the second direction DR2and a first electrode branch portion RM1_B branching from the firstelectrode stem portion RM1_S in the first direction DR1. The secondelectrode line RM2 may include a second electrode stem portion RM2_Sextending in the second direction DR2 and a second electrode branchportion RM2_B branching from the second electrode stem portion RM2_S inthe first direction DR1. The first electrode branch portion RM1_Bbranches toward the second side of the first direction DR1, is spacedapart from the second electrode stem portion RM2_S, and overlaps thefirst wiring horizontal portion VDL_H. The second electrode branchportion RM2_B branches toward the first side of the first direction DR1,is spaced apart from the first electrode stem portion RM1_S, andoverlaps the second wiring horizontal portion VSL_H.

In some embodiments, the electrode lines RM1 and RM2 may be utilized togenerate an electric field for placing (arranging) the light emittingelements ED, by transmitting alignment signals to the electrodes RME1and RME2 in each emission area EMA1, EMA2 or EMA3. The first electrodeline RM1 and the second electrode line RM2 including the electrode stemportions RM1_S and RM2_S may be provided across a plurality of pixelsPX. The electrode lines RM1 and RM2 may be connected to the firstelectrode RME1 and the second electrode RME2 of each subpixel PXn. Whenalignment signals are transmitted to the electrode lines RM1 and RM2, anelectric field may be generated on the electrodes RME1 and RME2. Thelight emitting elements ED may be sprayed onto the electrode lines RM1and RM2 through an inkjet printing process. When ink containing thelight emitting elements ED is sprayed onto the electrode lines RM1 andRM2, alignment signals are transmitted to the electrode lines RM1 andRM2 to generate an electric field. The light emitting elements ED may beplaced (arranged) on the electrodes RME1 and RME2 by the electric fieldformed between the electrode lines RM1 and RM2. For example, the lightemitting elements ED dispersed in the ink may be aligned on theelectrodes RME1 and RME2 by a dielectrophoretic force due to thegenerated electric field.

In some embodiments in which each electrode line RM1 or RM2 includes theelectrode stem portion RM1_S or RM2_S and the electrode branch portionRM1_B or RM2_B branching from the electrode stem portion RM1_S or RM2_S,the first electrodes RME1 and the second electrodes RME2 may beconnected to the first electrode branch portion RM1_B and the secondelectrode branch portion RM2_B, respectively. During a manufacturingprocess of the display device 10, the alignment signals transmitted tothe electrode lines RM1 and RM2 may be transmitted to the electrodesRME1 and RME2, and the light emitting elements ED may be placed(arranged) by the electric field generated on the electrodes RME1 andRME2. Then, a process of separating the first electrodes RME1 and thefirst electrode branch portion RM1_B may be performed, and thus thefirst electrode RME1 may be connected only to the first transistor T1connected to each subpixel PXn. The second electrodes RME2 may remainconnected to the second electrode branch portion RM2_B and may receivethe second power supply voltage from the second electrode line RM2connected to the second voltage wiring VSL.

For example, when alignment voltages applied to the electrode lines RM1and RM2 are different from voltages applied to wirings under theelectrode lines RM1 and RM2 (for example, the voltage wirings VDL andVSL of the third conductive layer), the intensity of an electric fieldgenerated by the alignment signals may be weak, and/or the direction ofthe electric field may be formed in an unwanted (orunsuitable/undesirable) area. This may increase the possibility that thelight emitting elements ED will be lost without being aligned at adesired position. In the display device 10 according to someembodiments, the voltage wirings VDL and VSL may be outside the emissionareas EMA1 through EMA3, and the light emitting elements ED may bealigned by utilizing the electrode lines RM1 and RM2 connected to thevoltage wirings VDL and VSL. Because the voltage wirings VDL and VSL areoutside the emission areas EMA1 through EMA3, the effect of the voltagewirings VDL and VSL on the direction or intensity of the electric fieldgenerated in the emission areas EMA1 through EMA3 can be reduced. Insome embodiments, because the electrode lines RM1 and RM2 are connectedto the voltage wirings VDL and VSL, an equipotential may be formedbetween them. Accordingly, the loss of the light emitting elements EDcan be prevented or reduced. The electrode lines RM1 and RM2 will bedescribed in more detail hereinbelow by further referring to thedrawings.

The electrodes RME1 and RME2 may be electrically connected to the lightemitting elements ED. In some embodiments, the electrodes RME1 and RME2may be connected to the third conductive layer to receive signals thatfacilitate the light emitting elements ED to emit light. The firstelectrodes RME1 and the second electrodes RME2 may be electricallyconnected to the third conductive layer respectively through firstelectrode contact holes CTD and second electrode contact holes CTSformed in the second electrode line RM2. For example, the firstelectrodes RME1 may include electrode contact portions CTP formed inportions where the first banks BNL1 are not provided in the emissionareas EMA1 through EMA3, and the electrode contact portions CTP maycontact the second capacitive electrodes CSE2 through the firstelectrode contact holes CTD penetrating the second interlayer insulatinglayer IL2. The second electrodes RME2 may be formed in areas where thesecond electrode line RM2 in the non-emission area overlaps the secondbank BNL2 and may contact the fifth conductive pattern DP5 through thesecond electrode contact holes CTS penetrating the second interlayerinsulating layer IL2. The first electrodes RME1 may be electricallyconnected to the first transistors T1 through the second capacitiveelectrodes CSE2 to receive the first power supply voltage, and thesecond electrodes RME2 may be electrically connected to the secondvoltage wiring VSL through the second electrode line RM2 and the fifthconductive pattern DP5 to receive the second power supply voltage.Because the first electrode RME1 is provided separately in each pixel PXand each subpixel PXn, the light emitting elements ED of differentsubpixels PXn may emit light individually (e.g., independently).

Each of the electrodes RME1 and RME2 and the electrode lines RM1 and RM2may include a conductive material having high reflectivity. For example,the electrodes RME1 and RME2 may each independently include a metal suchas silver (Ag), copper (Cu) and/or aluminum (Al) as a material havinghigh reflectivity, or may be an alloy including aluminum (Al), nickel(Ni) and/or lanthanum (La). Each of the electrodes RME1 and RME2 mayreflect light, which travels toward a side surface of a first bank BNL1after being emitted from the light emitting elements ED, toward aboveeach subpixel PXn.

However, the present disclosure is not limited thereto, and each of theelectrodes RME1 and RME2 may further include a transparent conductivematerial. For example, the electrodes RME1 and RME2 may eachindependently include a material such as ITO, IZO and/or ITZO. In someembodiments, each of the electrodes RME1 and RME2 may have a structurein which a transparent conductive material and a metal layer having highreflectivity are each stacked in one or more layers, or may be formed asa single layer including the transparent conductive material and themetal layer. For example, each of the electrodes RME1 and RME2 may havea stacked structure of ITO/Ag/ITO, ITO/Ag/IZO, or ITO/Ag/ITZO/IZO.

A first insulating layer PAS1 may be provided on the electrodes RME1 andRME2 and the first banks BNL1. The first insulating layer PAS1 may coverthe first banks BNL1 and the first electrodes RME1 and the secondelectrodes RME2, but may partially expose upper surfaces of the firstelectrodes RME1 and the second electrodes RME2. Openings may be formedin the first insulating layer PAS1 to expose a portion of the uppersurface of each electrode RME1 or RME2 which is on the first bank BNL1,and the contact electrodes CNE1 and CNE2 may contact the electrodes RME1and RME2 through the formed openings.

In some embodiments, the first insulating layer PAS1 may be stepped,such that a portion of an upper surface of the first insulating layerPAS1 is recessed between the first and second electrodes RME1 and RME2.When the first insulating layer PAS1 covers the first electrodes RME1and the second electrodes RME2, it may have a step between them.However, the present disclosure is not limited thereto. The firstinsulating layer PAS1 may protect the first electrodes RME1 and thesecond electrodes RME2 while insulating them from each other. In someembodiments, the first insulating layer PAS1 may prevent (or reduce) thelight emitting elements ED on the first insulating layer PAS1 fromdirectly contacting other members and thus being damaged.

The second bank BNL2 may be provided on the first insulating layer PAS1.The second bank BNL2 may include portions extending in the firstdirection DR1 and the second direction DR2 to form a lattice pattern inplan view. The second bank BNL2 may be at the boundary of each subpixelPXn to separate neighboring subpixels PXn. In some embodiments, thesecond bank BNL2 may surround the emission area EMA1, EMA2 or EMA3 andthe cut area CBA in each subpixel PXn to separate them from each other.Of the portions of the second bank BNL2 extending in the seconddirection DR2, a portion between the emission areas EMA1 through EMA3and a portion between the cut areas CBA may have the same width.Accordingly, a gap between the cut areas CBA may be, but is not limitedto, equal to a gap between the emission areas EMA1 through EMA3.

The second bank BNL2 may be formed to have a greater height in the thirddirection DR3 than the first banks BNL1. The second bank BNL2 mayprevent or reduce ink from overflowing to adjacent subpixels PXn in aninkjet printing process of the manufacturing process of the displaydevice 10. Therefore, the second bank BNL2 may separate inks in whichdifferent light emitting elements ED are dispersed for differentsubpixels PXn, so that the inks are not mixed with each other. As onefirst bank BNL1 is provided over subpixels PXn neighboring in the firstdirection DR1, a portion among the portions of the second bank BNL2extending the second direction DR2 may also be on the first bank BNL1.Like the first banks BNL1, the second bank BNL2 may include polyimide(PI), but the present disclosure is not limited thereto.

The light emitting elements ED may be on the first insulating layerPAS1. The light emitting elements ED may be spaced apart from each otheralong the second direction DR2 in which each electrode RME1 and RME2extends, and may be aligned substantially parallel to each other. Thelight emitting elements ED may extend in a direction, and the directionin which each electrode RME1 and RME2 extends and the direction in whichthe light emitting elements ED extend may be substantially perpendicularto each other. However, the present disclosure is not limited thereto,and the light emitting elements ED may also extend obliquely to thedirection in which each electrode RME1 and RME2 extends.

Each light emitting element ED may include semiconductor layers dopedwith different conductivity types (e.g., a p-type or an n-type). Eachlight emitting element ED including the semiconductor layers may beoriented such that an end of the light emitting element ED faces in aspecific (or set) direction according to the direction of an electricfield generated on the electrodes RME1 and RME2. In some embodiments,each light emitting element ED may include a light emitting layer 36(see FIG. 13) to emit light of a specific (or set) wavelength band. Thelight emitting elements ED in each subpixel PXn may emit light ofdifferent wavelength bands according to the material that forms thelight emitting layer 36. However, the present disclosure is not limitedthereto, and the light emitting elements ED in each of the subpixels PXnmay also emit light of the same color.

The light emitting elements ED may be on the electrodes RME1 and RME2between the first banks BNL1. For example, a first end of each lightemitting element ED may be on the first electrode RME1, and a second endmay be on the second electrode RME2. A length of each light emittingelement ED in the first direction DR1 may be greater than the gapbetween the first electrode RME1 and the second electrode RME2 in thefirst direction DR1, and both ends of the light emitting element ED maybe on the first electrode RME1 and the second electrode RME2,respectively.

Each light emitting element ED may include a plurality of layersextending in a direction perpendicular to an upper surface of the firstsubstrate SUB. The direction in which the light emitting elements ED ofthe display device 10 extend may be parallel to the first substrate SUB,and a plurality of semiconductor layers included in each light emittingelement ED may be sequentially stacked along a direction parallel to theupper surface of the first substrate SUB. However, the presentdisclosure is not limited thereto. In some embodiments, when each lightemitting element ED has a different structure, the semiconductor layersmay be stacked in the direction perpendicular to the first substrateSUB.

Both ends of each light emitting element ED may contact the contactelectrodes CNE1 and CNE2, respectively. For example, an insulating film38 (see FIG. 13) might not be formed on end surfaces of each lightemitting element ED in the direction in which each light emittingelement ED extends, thereby partially exposing the semiconductor layers.The exposed semiconductor layers may contact the contact electrodes CNE1and CNE2. However, the present disclosure is not limited thereto. Insome embodiments, at least a portion of the insulating film 38 of eachlight emitting element ED may be removed to partially expose sidesurfaces of both ends of the semiconductor layers. The exposed sidesurfaces of the semiconductor layers may directly contact the contactelectrodes CNE1 and CNE2.

A second insulating layer PAS2 may be partially on the light emittingelements ED. For example, the second insulating layer PAS2 may partiallysurround an outer surface of each light emitting element ED but notcover the first end and the second end of each light emitting elementED. The contact electrodes CNE1 and CNE2 may respectively contact bothends of each light emitting element ED not covered by the secondinsulating layer PAS2. Of the second insulating layer PAS2, a portion onthe light emitting elements ED may extend in the second direction DR2 onthe first insulating layer PAS1 in plan view to form a linear or islandpattern in each subpixel PXn. The second insulating layer PAS2 mayprotect the light emitting elements ED while fixing (e.g., stabilizing)the light emitting elements ED in the manufacturing process of thedisplay device 10.

During the manufacturing process of the display device 10, a cuttingprocess for forming each electrode RME1 or RME2—by forming electrodelines and then separating the electrode lines—may be performed after thesecond insulating layer PAS2 is formed. The second insulating layer PAS2may be omitted from the cut areas CBA but may be only in the emissionareas EMA1 through EMA3. In the cut areas CBA, only the electrodes RME1and RME2 and the first insulating layer PAS1 may be positioned. In thecut areas CBA, the electrodes RME1 and RME2 may be spaced apart toexpose the second interlayer insulating layer IL2, and the firstinsulating layer PAS1 may be separately provided on the separatedelectrodes RME1 and RME2.

A plurality of contact electrodes CNE1 and CNE2 may be on the secondinsulating layer PAS2. A first contact electrode CNE1 and a secondcontact electrode CNE2 of the contact electrodes CNE1 and CNE2 may be ona portion of each first electrode RME1 and a portion of each secondelectrode RME2, respectively. The first contact electrode CNE1 may be oneach first electrode RME1, and the second contact electrode CNE2 may beon each second electrode RME2. The first contact electrode CNE1 and thesecond contact electrode CNE2 may extend in the second direction DR2.The first contact electrode CNE1 and the second contact electrode CNE2may be spaced apart from each other in the first direction DR1 to faceeach other, and may form linear patterns in the emission area EMA1, EMA2or EMA3 of each subpixel PXn.

In some embodiments, widths of the first and second contact electrodesCNE1 and CNE2 measured in a direction (e.g., in the first direction DR1)may be smaller than widths of the first and second electrodes RME1 andRME2 measured in the direction (e.g., in the first direction DR1). Thefirst contact electrode CNE1 and the second contact electrode CNE2 mayrespectively contact the first end and the second end of each lightemitting element ED and may be only on a portion of the upper surfacesof the first and second electrodes RME1 and RME2.

The contact electrodes CNE1 and CNE2 may contact the light emittingelements ED and the electrodes RME1 and RME2. The semiconductor layersmay be exposed on both end surfaces of each light emitting element ED inthe direction in which each light emitting element ED extends, and thefirst contact electrode CNE1 and the second contact electrode CNE2 maycontact each light emitting element ED at the end surfaces where thesemiconductor layers are exposed. The first end of each light emittingelement ED may be electrically connected to the first electrode RME1through the first contact electrode CNE1, and the second end may beelectrically connected to the second electrode RME2 through the secondcontact electrode CNE2.

Although one first contact electrode CNE1 and one second contactelectrode CNE2 in one subpixel PXn are illustrated in the drawings, thepresent disclosure is not limited thereto. The number of the firstcontact electrodes CNE1 and the second contact electrodes CNE2 may varyaccording the number of the first electrodes RME1 and the secondelectrodes RME2 in each subpixel PXn.

The contact electrodes CNE1 and CNE2 may include a conductive materialsuch as ITO, IZO, ITZO, and/or aluminum (Al). For example, the contactelectrodes CNE1 and CNE2 may each independently include a transparentconductive material, and light emitted from the light emitting elementsED may pass through the contact electrodes CNE1 and CNE2 and proceedtoward the electrodes RME1 and RME2, but the present disclosure is notlimited thereto.

In some embodiments, an insulating layer may be further provided on thecontact electrodes CNE1 and CNE2 and the second bank BNL2 to cover them.The insulating layer may be entirely on the first substrate SUB toprotect members positioned on the first substrate SUB from the externalenvironment.

Each of the first insulating layer PAS1 and the second insulating layerPAS2 described above may include an inorganic insulating material or anorganic insulating material. In some embodiments, each of the firstinsulating layer PAS1 and the second insulating layer PAS2 may includean inorganic insulating material such as silicon oxide (SiOx), siliconnitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al₂O₃),and/or aluminum nitride (AlN). In some embodiments, each of the firstinsulating layer PAS1 and the second insulating layer PAS2 may includean organic insulating material such as acrylic resin, epoxy resin,phenolic resin, polyamide resin, polyimide resin, unsaturated polyesterresin, polyphenylene resin, polyphenylene sulfide resin,benzocyclobutene, cardo resin, siloxane resin, silsesquioxane resin,polymethyl methacrylate, polycarbonate, and/or polymethylmethacrylate-polycarbonate synthetic resin. However, the presentdisclosure is not limited thereto.

As described above, the display device 10 according to some embodimentsmay include the voltage wirings VDL and VSL outside the emission areasEMA1 through EMA3 of each pixel PX, and the electrode lines RM1 and RM2overlapping the voltage wirings VDL and VSL.

FIG. 10 is a schematic view illustrating the arrangement of voltagewirings, electrodes, and electrode lines in one pixel PX of the displaydevice 10 according to some embodiments. FIG. 11 is a cross-sectionalview taken along lines Q7-Q7′ and Q8-Q8′ of FIG. 10. FIG. 11 illustratesa cross-section of portions where the voltage wirings VDL and VSL andthe electrode lines RM1 and RM2 are connected.

Referring to FIGS. 10 and 11, in the display device 10, the voltagewirings VDL and VSL including the wiring vertical portions VDL_V andVSL_V and the wiring horizontal portions VDL_H and VSL_H may be outsidethe emission areas EMA1 through EMA3 of each pixel PX. The voltagewirings VDL and VSL may overlap the second bank BNL2 in the thicknessdirection and may be adjacent to a boundary between adjacent pixels PX.The voltage wirings VDL and VSL may be omitted from inside the emissionareas EMA1 through EMA3 of the pixel PX, or between the emission areasEMA1 through EMA3, but may surround the emission areas EMA1 throughEMA3. One voltage wiring VDL and/or VSL may be connected to at least onepixel PX, and the subpixels PXn of each pixel PX may share the samevoltage wiring VDL and/or VSL.

The first electrode line RM1 and the second electrode line RM2 may alsooverlap the voltage wirings VDL and VSL and surround the emission areasEMA1 through EMA3. As described above, the electrode lines RM1 and RM2may respectively include the electrode stem portions RM1_S and RM2_Soverlapping the wiring vertical portions VDL_V and VSL_V in thethickness direction and the electrode branch portions RM1_B and RM2_Boverlapping the wiring horizontal portions VDL_H and VSL_H in thethickness direction.

The first electrode stem portion RM1_S may contact the first conductivepattern DP1 through a plurality of third electrode contact holes CTApenetrating the second interlayer insulating layer IL2, and thus may beconnected to the first voltage wiring VDL. The second electrode stemportion RM2_S may contact the fifth conductive pattern DP5 through aplurality of second electrode contact holes CTS penetrating the secondinterlayer insulating layer IL2, and thus may be connected to the secondvoltage wiring VSL.

During the manufacturing process of the display device 10, the firstelectrode branch portion RM1_B of the first electrode line RM1 may beconnected to the first electrode RME1 in each subpixel PXn. Because thesecond electrodes RME2 are also connected to the second electrode branchportion RM2_B, the first electrode line RM1 and the second electrodeline RM2 in one pixel PX may be substantially simultaneously (orconcurrently) connected to the electrodes RME1 and RME2 in a pluralityof subpixels PXn.

Alignment signals may be directly transmitted to the electrode stemportions RM1_S and RM2_S and then transmitted to the electrodes RME1 andRME2 through the electrode branch portions RM1_B and RM2_B to formelectric fields on the electrodes RME1 and RME2. The subpixels PXn ofeach pixel PX may share the same electrode lines RM1 and RM2, and theelectrodes RME1 and RME2 may be connected to the electrode lines RM1 andRM2. Thus, the electric fields may be substantially simultaneously (orconcurrently) generated.

In some embodiments, the first voltage wiring VDL and the second voltagewiring VSL may be connected to the electrode stem portions RM1_S andRM2_S to receive the alignment signals. Accordingly, the same voltagesmay be applied to the electrode lines RM1 and RM2 and to the voltagewirings VDL and VSL under the electrode lines RM1 and RM2, to form anequipotential. When the voltage wirings VDL and VSL form anequipotential with the electrode lines RM1 and RM2 without beingpositioned across the inside of the emission areas EMA1 through EMA3, anelectric field might not be generated in an unwanted (or undesirable)area by the voltage wirings VDL and VSL, and the movement of the lightemitting elements ED out of place may be prevented or reduced.

After the placement of the light emitting elements ED, a process ofseparating the first electrodes RME1 from the first electrode line RM1is performed to drive each subpixel PXn separately. In some embodiments,the first electrodes RME1 may be separated and spaced apart from thefirst electrode branch portion RM1_B in the cut areas CBA. When thefirst electrodes RME1 are separated from the first electrode line RM1,they may receive the first power supply voltage of the first voltagewiring VDL from the first transistors T1 connected through the firstelectrode contact holes CTD. On the other hand, the second electrodesRME2 might not be separated from the second electrode line RM2 and mayreceive the second power supply voltage of the second voltage wiring VSLconnected through the second electrode contact holes CTS.

In the display device 10 according to some embodiments, the firstelectrode line RM1 and the first voltage wiring VDL may be electricallyconnected to each other, and the second electrode line RM2 and thesecond voltage wiring VSL may be electrically connected to each otherduring the manufacturing process. Because they are arranged in a meshstructure over the entire display area DPA, a voltage drop can beprevented or reduced. In some embodiments, the subpixels PXn included ineach pixel PX may share the same voltage wirings VDL and VSL and thesame electrode lines RM1 and RM2, and the display device 10 can reducethe number of wirings required per unit area. Therefore, an ultra-highresolution display device can be implemented.

When the voltage wirings VDL and VSL have a mesh structure, the voltagewirings VDL and VSL and the electrode lines RM1 and RM2 are provided atthe boundaries of pixels PX adjacent in the first direction DR1 and thesecond direction DR2. When different voltage wirings VDL and VSL anddifferent electrode lines RM1 and RM2 are included in one pixel PX, thearrangement structure of the subpixels PXn in each pixel PX may be thesame.

FIG. 12 is a schematic view illustrating the arrangement of the voltagewirings VDL and VSL and the electrode lines RM1 and RM2 in a pluralityof pixels PX of the display device 10 according to some embodiments.FIG. 12 schematically illustrates the pixels PX separated by the voltagewirings VDL and VSL and the electrode lines RM1 and RM2 and thearrangement of the electrodes RME1 and RME2 and the light emittingelements ED in the subpixels PXn of each pixel PX.

Referring to FIG. 12, the first voltage wiring VDL and the secondvoltage wiring VSL may extend in the first direction DR1 and the seconddirection DR2 and may be in each pixel PX. In the same way, the firstelectrode line RM1 and the second electrode line RM2 may includeportions extending in the first direction DR1 and the second directionDR2 and may overlap the voltage wirings VDL and VSL in each pixel PX.

In the display area DPA, a plurality of pixel columns PXC1 and PXC2 anda plurality of pixel rows PXR1 through PXR3 may be arranged. In thedrawing, the pixels PX in a first pixel column PXC1, a second pixelcolumn PXC2, a first pixel row PXR1, a second pixel row PXR2, and athird pixel row PXR3 are illustrated. In the first pixel column PXC1, afirst pixel PX#1 in the first pixel row PXR1, a second pixel PX#2 in thesecond pixel row PXR2, and a third pixel PX#3 in the third pixel rowPXR3 are provided. In the second pixel column PXC2, a fourth pixel PX#4in the first pixel row PXR1, a fifth pixel PX#5 in the second pixel rowPXR2, and a sixth pixel PX#6 in the third pixel row PXR3 are provided.

In the current example, the structures of the voltage wirings VDL andVSL and the electrode lines RM1 and RM2 may be repeated on apixel-by-pixel basis. As pixels in the same pixel column PXC, the firstpixel PX#1, the second pixel PX#2 and the third pixel PX#3 of the firstpixel column PXC1 may share the same wiring vertical portions VDL_V andVSL_V. Similarly, the fourth pixel PX#4, the fifth pixel PX#5 and thesixth pixel PX#6 of the second pixel column PXC2 may also share the samewiring vertical portions VDL_V and VSL_V. In some embodiments, as pixelsin the same pixel row PXR, the first pixel PX#1 and the fourth pixelPX#4 of the first pixel row PXR1 may share the same wiring horizontalportions VDL_H and VSL_H. Similarly, the second pixel PX#2 and the fifthpixel PX#5 of the second pixel row PXR2, and the third pixel PX#3 andthe sixth pixel PX#6 of the third pixel row PXR3, may share the samewiring horizontal portions VDL_H and VSL_H, respectively. However,different wiring vertical portions VDL_V and VSL_V and different wiringhorizontal portions VDL_H and VSL_H may be in pixels PX that are both indifferent pixel columns PXC and in different pixel rows PXR.

In the case of the first electrode line RM1 and the second electrodeline RM2, pixels in the same pixel column PXC may share the electrodestem portions RM1_S and RM2_S which are different from the electrodestem portions RM1_S and RM2_S shared by pixels in a different pixelcolumn PXC. However, pixels in the same pixel row PXR may have differentelectrode branch portions RM1_B and RM2_B.

In some embodiments in which the voltage wirings VDL and VSL and theelectrode lines RM1 and RM2 are in each pixel PX, the arrangement of theelectrodes RME1 and RME2 and the arrangement of the light emittingelements ED may be the same in the first through sixth pixels PX#1through PX#6. The second electrode line RM2 may be on the upper side ofthe center of each pixel PX, and the first electrode line RM1 may be onthe lower side of the center of each pixel PX. In each subpixel PXn, thesecond electrode RME2 may be on the left side, and the first electrodeRME1 may be on the right side. Each light emitting element ED mayinclude a plurality of semiconductor layers and the light emitting layer36 between them, and the first end of the light emitting element EDadjacent to the light emitting layer 36 may be defined. The lightemitting elements ED may be placed such that their respective first endslie on the first electrode RME1 to which the first power supply voltageis applied. As in the example shown in FIG. 12, the light emittingelements ED of the first through sixth pixels PX#1 through PX#6 may beplaced such that their first ends face the first side of the directionDR1.

In the display device 10, because the voltage wirings VDL and VSL andthe electrode lines RM1 and RM2 extending in the first direction DR1 andthe second direction DR2 are in each pixel PX, the arrangement of theelectrodes RME1 and RME2 and the arrangement of the light emittingelements ED may be the same in each pixel PX. However, the presentdisclosure is not limited thereto. In some embodiments, pixels PXadjacent to each other may share the voltage wirings VDL and VSL or theelectrode lines RM1 and RM2, and a plurality of pixels PX may includedifferent types (or kinds) of pixels which are different in thedirection in which the light emitting elements ED of each subpixel PXnface. This will be described with reference to other embodiments.

FIG. 13 is a schematic view of a light emitting element ED according tosome embodiments.

The light emitting element ED may be a light emitting diode. Forexample, the light emitting element ED may be an inorganic lightemitting diode having a size of micrometers or nanometers and made of aninorganic material. When an electric field is formed in a specific (orset) direction between two electrodes facing each other, the inorganiclight emitting diode may be aligned between the two electrodes in whichpolarities are formed. The light emitting element ED may be alignedbetween the electrodes by the electric field formed on the twoelectrodes.

The light emitting element ED according to some embodiments may extendin one direction. The light emitting element ED may be shaped like arod, a wire, a tube, and/or the like. In some embodiments, the lightemitting element ED may be shaped like a cylinder or a rod. However, theshape of the light emitting element ED is not limited thereto, and thelight emitting element ED may have various suitable shapes includingpolygonal prisms, such as a cube, a rectangular parallelepiped and/or ahexagonal prism, and may have a shape extending in a direction andhaving a partially inclined outer surface. A plurality of semiconductorsincluded in the light emitting element ED may be sequentially arrangedor stacked along the one direction.

The light emitting element ED may include a semiconductor layer dopedwith impurities of any conductivity type (e.g., a p type or an n type).The semiconductor layer may receive an electrical signal from anexternal power source and emit light of a specific (or set) wavelengthband.

Referring to FIG. 13, the light emitting element ED may include a firstsemiconductor layer 31, a second semiconductor layer 32, the lightemitting layer 36, an electrode layer 37, and the insulating film 38.

The first semiconductor layer 31 may be an n-type semiconductor. Forexample, when the light emitting element ED is to emit light in a bluewavelength band, the first semiconductor layer 31 may include asemiconductor material having a chemical formula ofAl_(x)Ga_(y)In_(1−x−y)N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1). The semiconductormaterial included in the first semiconductor layer 31 may be, forexample, one or more selected from n-type doped AlGaInN, GaN, AlGaN,InGaN, AlN, and InN. The first semiconductor layer 31 may be doped withan n-type dopant, and the n-type dopant may be, for example, Si, Ge,and/or Sn. In some embodiments, the first semiconductor layer 31 may ben-GaN doped with n-type Si. A length of the first semiconductor layer 31may be in the range of, but not limited to, about 1.5 to about 5 μm.

The second semiconductor layer 32 may be on the light emitting layer 36.The second semiconductor layer 32 may be a p-type semiconductor. Forexample, when the light emitting element ED is to emit light in a blueor green wavelength band, the second semiconductor layer 32 may includea semiconductor material having a chemical formula ofAl_(x)Ga_(y)In_(1−x−y)N (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1). The semiconductormaterial included in the second semiconductor layer 32 may be, forexample, one or more selected from p-type doped AlGaInN, GaN, AlGaN,InGaN, AlN, and InN. The second semiconductor layer 32 may be doped witha p-type dopant, and the p-type dopant may be, for example, Mg, Zn, Ca,Se, and/or Ba. In some embodiments, the second semiconductor layer 32may be p-GaN doped with p-type Mg. A length of the second semiconductorlayer 32 may be in the range of, but not limited to, about 0.05 to about0.10 μm.

Although each of the first semiconductor layer 31 and the secondsemiconductor layer 32 is composed of one layer in the drawing, thepresent disclosure is not limited thereto. According to embodiments,each of the first semiconductor layer 31 and the second semiconductorlayer 32 may include more layers, for example, may further include aclad layer and/or a tensile strain barrier reducing (TSBR) layer,depending on the material of the light emitting layer 36.

The light emitting layer 36 may be between the first semiconductor layer31 and the second semiconductor layer 32. The light emitting layer 36may include a material having a single or multiple quantum wellstructure. When the light emitting layer 36 includes a material having amultiple quantum well structure, it may have a structure in which aplurality of quantum layers and a plurality of well layers arealternately stacked. The light emitting layer 36 may emit light throughcombination of electron-hole pairs according to electrical signalsreceived through the first semiconductor layer 31 and the secondsemiconductor layer 32. For example, when the light emitting layer 36 isto emit light in the blue wavelength band, it may include a materialsuch as AlGaN and/or AlGaInN. In some embodiments, when the lightemitting layer 36 has a multiple quantum well structure in which aquantum layer and a well layer are alternately stacked, the quantumlayer may include a material such as AlGaN and/or AlGaInN, and the welllayer may include a material such as GaN and/or AlInN. In someembodiments, the light emitting layer 36 may include AlGaInN as aquantum layer and AlInN as a well layer to emit blue light whose centralwavelength band is in the range of about 450 to about 495 nm.

However, the present disclosure is not limited thereto, and the lightemitting layer 36 may also have a structure in which a semiconductormaterial having a large band gap energy and a semiconductor materialhaving a small band gap energy are alternately stacked, or may includedifferent group 3 to 5 (Group III to V) semiconductor materialsdepending on the wavelength band of light that the light emitting layer36 is to emit. Light emitted from the light emitting layer 36 is notlimited to light in the blue wavelength band. In some embodiments, thelight emitting layer 36 may emit light in a red or green wavelengthband. A length of the light emitting layer 36 may be in the range of,but not limited to, about 0.05 to about 0.10 μm.

Light emitted from the light emitting layer 36 may be radiated not onlythrough the longitudinal outer surface of the light emitting element EDbut also through both side surfaces. The direction of light emitted fromthe light emitting layer 36 is not limited to one direction.

The electrode layer 37 may be an ohmic contact electrode. However, thepresent disclosure is not limited thereto, and the electrode layer 37may also be a Schottky contact electrode. The light emitting element EDmay include at least one electrode layer 37. Although the light emittingelement ED includes one electrode layer 37 in FIG. 13, the presentdisclosure is not limited thereto. In some embodiments, the lightemitting element ED may include more electrode layers 37, or theelectrode layer 37 may be omitted. The following description of thelight emitting element ED may be applied even if the light emittingelement ED includes a different number of electrode layers 37 and/orfurther includes other structures.

When the light emitting element ED is electrically connected to anelectrode or a contact electrode in the display device 10 according tosome embodiments, the electrode layer 37 may reduce the resistancebetween the light emitting element ED and the electrode and/or thecontact electrode. The electrode layer 37 may include a conductivemetal. For example, the electrode layer 37 may include at least oneselected from aluminum (Al), titanium (Ti), indium (In), gold (Au),silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indiumtin zinc oxide (ITZO). In some embodiments, the electrode layer 37 mayinclude an n-type or p-type doped semiconductor material. The electrodelayer 37 may include the same material or different materials, but thepresent disclosure is not limited thereto.

The insulating film 38 surrounds outer surfaces of a plurality ofsemiconductor layers and a plurality of electrode layers. In someembodiments, the insulating film 38 may surround an outer surface of atleast the light emitting layer 36 and extend in the direction in whichthe light emitting element ED extends. The insulating film 38 mayprotect the above-described members (e.g., layers) of the light emittingelement ED. For example, the insulating film 38 may surround sidesurfaces of the above-described members (e.g., layers) but may exposeboth ends of the light emitting element ED in a longitudinal direction.

In the drawing, the insulating film 38 extends in the longitudinaldirection of the light emitting element ED to cover from a side surfaceof the first semiconductor layer 31 to a side surface of the electrodelayer 37. However, the present disclosure is not limited thereto, andthe insulating film 38 may also cover outer surfaces of only somesemiconductor layers, as well as the light emitting layer 36, or maycover only a portion of an outer surface of the electrode layer 37 topartially expose the outer surface of each electrode layer 37. In someembodiments, an upper surface of the insulating film 38 may be roundedin cross section (e.g., may have a round cross section) in an areaadjacent to at least one end of the light emitting element ED.

A thickness of the insulating film 38 may be in the range of, but notlimited to, about 10 nm to about 1.0 μm. For example, the thickness ofthe insulating film 38 may be about 40 nm.

The insulating film 38 may include a material having insulatingproperties, such as silicon oxide (SiOx), silicon nitride (SiNx),silicon oxynitride (SiOxNy), aluminum nitride (AlNx), and/or aluminumoxide (AlOx). Accordingly, it can prevent or reduce an electrical shortcircuit that may occur when the light emitting layer 36 directlycontacts an electrode that transmits an electrical signal to the lightemitting element ED. In some embodiments, because the insulating film 38protects the outer surface of the light emitting element ED includingthe light emitting layer 36, a reduction in luminous efficiency can beprevented or reduced.

In some embodiments, an outer surface of the insulating film 38 may betreated. The light emitting elements ED dispersed in a predetermined inkmay be sprayed onto electrodes and then aligned. Here, the surface ofthe insulating film 38 may be hydrophobic or hydrophilic-treated so thatthe light emitting element ED is kept separate in the ink without beingagglomerated with other adjacent light emitting elements ED.

A length h of the light emitting element ED may be in the range of about1 to about 10 μm, or 2 to 6 μm, and may, for example, be in the range ofabout 3 to about 5 μm. In some embodiments, a diameter of the lightemitting element ED may be in the range of about 30 to about 700 nm, andan aspect ratio of the light emitting element ED may be about 1.2 toabout 100. However, the present disclosure is not limited thereto, and aplurality of light emitting elements ED included in the display device10 may also have different diameters according to a difference in thecomposition of the light emitting layer 36. The diameter of the lightemitting element ED may be, for example, about 500 nm.

A process of manufacturing the display device 10 according to someembodiments will now be described by further referring to otherdrawings.

FIGS. 14 through 16 are plan views sequentially illustrating the processof manufacturing the display device 10 according to some embodiments. InFIGS. 14 through 16, a process of forming the electrode lines RM1 andRM2 and the electrodes RME1 and RME2, and then separating the electrodelines RM1 and RM2 from the electrodes RME1 and RME2 after aligning thelight emitting elements ED, is illustrated.

First, referring to FIGS. 14 and 15, in the manufacturing process of thedisplay device 10, the electrode lines RM1 and RM2 are formed, andsignals are transmitted to the electrode lines RM1 and RM2 to align thelight emitting elements ED in the emission area EMA1, EMA2 or EMA3 ofeach subpixel PXn. During the manufacturing process, the electrodebranch portions RM1_B and RM2_B may be formed to be connected to thefirst electrodes RME1 and the second electrodes RME2, respectively. Thefirst electrodes RME1 may extend in the direction DR2 beyond the cutareas CBA (see FIG. 16) and may be connected to the first electrodebranch portion RM1_B outside the emission areas EMA1 through EMA3. Theelectrode stem portions RM1_S and RM2_S may extend in the seconddirection DR2 to the pad area PDA outside the display area DPA. Theelectrode stem portions RM1_S and RM2_S may be connected to the wiringpads of the pad area PDA to receive alignment signals from an externaldevice.

In some embodiments, the light emitting elements ED dispersed in ink maybe prepared and sprayed to the emission area EMA1, EMA2 or EMA3 of eachsubpixel PXn through an inkjet printing process. The second bank BNL2may prevent or reduce the risk of the ink overflowing to the emissionareas EMA1 through EMA3 of other neighboring subpixels PXn. When the inkis sprayed to the emission areas EMA1 through EMA3, alignment signalsare transmitted to the first electrode line RM1 and the second electrodeline RM2 to generate an electric field on the electrodes RME1 and RME2.The light emitting elements ED dispersed in the ink are changed in theirposition and orientation direction by an electrophoretic force due tothe electric field. Thus, both ends of each light emitting element EDmay be respectively on different electrodes RME1 and RME2. In someembodiments, once the light emitting elements ED are placed, the secondinsulating layer PAS2 is formed to fix the light emitting elements ED.

During the manufacturing process of the display device 10, alignmentsignals for aligning the light emitting elements ED may be transmittedto the first electrode line RM1 and the second electrode line RM2. Thefirst electrodes RME1 and the second electrodes RME2 provided in aplurality of subpixels PXn may be connected to the same electrode linesRM1 and RM2, respectively, and the signals for aligning the lightemitting elements ED may be substantially simultaneously (orconcurrently) transmitted to the subpixels PXn.

In some embodiments, because the electrode lines RM1 and RM2 and thevoltage wirings VDL and VSL are outside the emission areas EMA1 throughEMA3 in each pixel PX, it is possible to prevent or reduce thegeneration of an electric field in an unwanted (or undesirable) area inthe emission areas EMA1 through EMA3 by wirings that otherwise may bearranged under the electrodes RME1 and RME2. The light emitting elementsED sprayed to the emission areas EMA1 through EMA3 may be placed at adesired position by an electric field generated on the electrodes RME1and RME2, and may be prevented (or protected) from being displaced to aposition other than the position on the electrodes RME1 and RME2 by anelectric field generated by the wirings that otherwise may be arrangedunder the electrodes RME1 and RME2.

In some embodiments, the first electrode line RM1 and the secondelectrode line RM2 may be connected to the first voltage wiring VDL andthe second voltage wiring VSL, respectively, and the voltage wirings VDLand VSL and the electrode lines RM1 and RM2 may form an equipotential inresponse to alignment signals transmitted to the electrode lines RM1 andRM2. In the display device 10, because the voltage wirings VDL and VSLunder the electrodes RME1 and RME2 have a different electric potential,it is possible to prevent or reduce a change in the direction andintensity of an electric field generated on the electrodes RME1 andRME2, and/or prevent or reduce an electric field from being generated inan unwanted (or undesirable) area by the wirings under the electrodesRME1 and RME2.

Next, referring to FIG. 16, the process of separating the firstelectrodes RME1 from the first electrode line RM1 in the cut areas CBAis performed. The separation process is achieved by removing a portionconnecting the first electrode RME1 and the first electrode branchportion RM1_B from each cut area CBA. As the first electrodes RME1 areseparated from the first electrode line RM1, they might not be directlyconnected to the first voltage wiring VDL, but may be connected to thefirst voltage wiring VDL through the first transistors T1. During themanufacturing process of the display device 10, an alignment signal isdirectly transmitted to the first electrodes RME1 through the firstelectrode line RM1. However, during the driving of the display device10, the first power supply voltage applied to the first voltage wiringVDL may be transmitted to the first electrode RME1 through the firsttransistor T1 of each subpixel PXn. For example, while an alignmentsignal is substantially simultaneously (or concurrently) transmitted tothe first electrodes RME1 in a plurality of subpixels PXn during themanufacturing process, each first electrode RME1 may be drivenindividually by the first transistor T1 of each subpixel PXn during thedriving of the display device 10.

In some embodiments, the contact electrodes CNE1 and CNE2 are formed tocontact the light emitting elements ED and the electrodes RME1 and RME2.Through the above processes, the display device 10 according to someembodiments may be manufactured. In the display device 10, the voltagewirings VDL and VSL may be placed outside the emission areas EMA1through EMA3 in each pixel PX and may be connected to the electrodelines RM1 and RM2. Therefore, the placement of the light emittingelements ED in an unwanted area can be prevented or reduced.

Other embodiments of the display device 10 will now be described withreference to other drawings.

FIG. 17 is a schematic plan view of a plurality of electrodes and aplurality of banks included in one pixel PX of a display device 10_1according to some embodiments. FIGS. 18 and 19 are plan viewsillustrating portion of a process of manufacturing the display device10_1 of FIG. 17. In FIGS. 17 through 19, only voltage wirings VDL andVSL, electrode lines RM1 and RM2, and electrodes RME1_1 and RME2_1 areillustrated for ease of description.

Referring to FIGS. 17 through 19, the display device 10_1 according tosome embodiments may include more electrodes RME1_1 and RME2_1 and morelight emitting elements ED in each subpixel PXn. For example, eachsubpixel PXn may include two first electrodes RME1_1 and two secondelectrodes RME2_1 arranged alternately. The current example is differentfrom the example of FIG. 7 in that more electrodes are provided in eachsubpixel PXn.

As more electrodes RME1_1 and RME2_1 are provided in each subpixel PXn,more first banks BNL1 may be provided. The first banks BNL1 may includea plurality of first sub banks BNL_A and a second sub bank BNL_B betweenthem. The first sub banks BNL_A may extend in the second direction DR2,like the first banks BNL1 of FIG. 7, and the first and second electrodesRME1_1 and RME2_1 may be on the first sub banks BNL_A, respectively. Thesecond sub bank BNL_B may be between the first sub banks BNL_A and mayhave a greater width than the first sub banks BNL_A. Differentelectrodes RME1_1 and RME2_1 may be on both sides of the second sub bankBNL_B in the first direction DR1 and may be spaced apart from each otheron the second sub bank BNL_B. However, the present disclosure is notlimited thereto, and the sub banks BNL_A and BNL_B may also havesubstantially the same width.

In each subpixel PXn, a plurality of first electrodes RME1_1 and aplurality of second electrodes RME2_1 may be provided. The firstelectrodes RME1_1 may extend in the second direction DR2 and may beconnected to each other through a connection portion adjacent to a cutarea CBA. Of the first electrodes RME1_1, any one first electrode RME1_1may be electrically connected to a first transistor T1 under the firstelectrode RME1_1 through a first electrode contact hole CTD. Althoughthe first electrode RME1_1 is illustrated in the drawings as not havingan electrode contact portion CTP, the present disclosure is not limitedthereto. The second electrodes RME2_1 may extend in the second directionDR2 and may be connected to a second electrode line RM2. The firstelectrodes RME1_1 and the second electrodes RME2_1 may be spaced apartfrom each other in the first direction DR1 and may be alternatelyarranged. Light emitting elements ED may be on each of the firstelectrodes RME1_1 and the second electrodes RME2_1. Because more lightemitting elements ED are provided in each subpixel PXn, the amount oflight emission per unit area may increase.

In some embodiments, in each subpixel PXn, a plurality of first contactelectrodes CNE1_1 and a plurality of second contact electrodes CNE2_1are provided. The first contact electrodes CNE1_1 may be on differentfirst electrodes RME1_1, respectively, and the second contact electrodesCNE2_1 may be on different second electrodes RME2_1, respectively. Thecontact electrodes CNE1_1 and CNE2_1 are the same as those describedabove.

Because the first electrodes RME1_1 are connected to each other throughthe connection portion, and the second electrodes RME2_1 are connectedto the second electrode line RM2, power supply voltages may besubstantially simultaneously (or concurrently) applied to the electrodesRME1_1 and RME2_1, respectively. Accordingly, the light emittingelements ED arranged on different first electrodes RME1_1 and differentsecond electrodes RME2_1 may be connected in parallel to each other.

A process of manufacturing the display device 10_1 according to thecurrent example is substantially the same as that described above withreference to FIGS. 14 through 16. The first electrodes RME1_1 may beformed to be connected to a first electrode line RM1, and then may beseparated from the first electrode line RM1 in the cut area CBA afterthe light emitting elements ED are placed. Here, if the first electrodesRME1_1 are separated from each other, a power supply voltage might notbe applied to the light emitting elements ED on any one first electrodeRME1_1. Therefore, the first electrodes RME1_1 separated in the cut areaCBA may be connected to each other.

FIG. 20 is a schematic plan view of a plurality of electrodes and aplurality of banks included in one pixel PX of a display device 10_2according to some embodiments.

Referring to FIG. 20, in the display device 10_2 according to someembodiments, electrodes RME1_2 and RME2_2 in each subpixel PXn mayextend in the first direction DR1 and may be spaced apart from eachother in the second direction DR2. Electrode lines RM1_2 and RM2_2 mayomit electrode branch portions RM1_B and RM2_B, respectively, and mayextend in the second direction DR2 in portions overlapping wiringvertical portions VDL_V and VSL_V. First electrodes RME1_2 may beseparated in a cut area CBA from a first electrode line RM1_2 extendingin the second direction DR2, and second electrodes RME2_2 may bedirectly connected to a second electrode line RM2_2 extending in thesecond direction DR2.

A plurality of voltage wirings VDL and VSL extend in the first directionDR1 and the second direction DR2, and the subpixels PXn in one pixel PXshare the same voltage wirings VDL and VSL. Therefore, the direction andarrangement of each subpixel PXn can be variously suitably changed. Thevoltage wirings VDL and VSL may be on the periphery of one pixel PX tosurround emission areas EMA1 through EMA3, and the emission areas EMA1through EMA3 may be arranged in various directions in the pixel PX. Thecurrent example is different from the example of FIG. 17 in that theelectrodes RME1_2 and RME2_2 extend in the first direction DR1 becausethe subpixels PXn in each pixel PX are arranged in the second directionDR2. Because the electrode lines RM1_2 and RM2_2 are connected to thevoltage wirings VDL and VSL through a first conductive pattern DP1 and afifth conductive pattern DP5 in portions extending in the seconddirection DR2, they may be connected in the same way as in the aboveexample even if the arrangement of the subpixels PX is changed. Otherdetails are the same as those described above, and thus a redundantdescription thereof is not provided.

FIG. 21 is a schematic plan view of a plurality of electrodes and aplurality of banks included in one pixel PX of a display device 10_3according to some embodiments.

Referring to FIG. 21, the display device 10_3 according to someembodiments may include electrodes RME1_3 through RME4_3 arranged ineach subpixel PXn and separated from each other. Each subpixel PXn mayinclude a third electrode RME3_3 between a first electrode RME1_3 and asecond electrode RME2_3, and a fourth electrode RME4_3 spaced apart fromthe third electrode RME3_3 with the second electrode RME2_3 interposedbetween them. The first electrode RME1_3 may be connected to a firsttransistor T1 through a first electrode contact hole CTD, and the secondelectrode RME2_3 may be connected to a second electrode line RM2. Thethird electrode RME3_3 and the fourth electrode RME4_3 might not beconnected to a circuit layer under them. The current example isdifferent from the example of FIG. 7 in that it further includes otherelectrodes separated from the first electrode RME1_3 and the secondelectrode RME2_3.

For example, the first electrode RME1_3 may be on a first sub bankBNL_A, and the second electrode RME2_3 may be on a side of a second subbank BNL_B. The third electrode RME3_3 may be on the other side of thesecond sub bank BNL_B, and the fourth electrode RME4_3 may be on anotherfirst sub bank BNL_A. The electrodes RME1_3 through RME4_3 may extend inthe second direction DR2 but may be spaced apart from each other in thefirst direction DR1, and light emitting elements ED may be provided onthem.

The first electrode RME1_3 and the fourth electrode RME4_3 may beconnected to a first electrode line RM1 and then separated from thefirst electrode line RM1 after an alignment process of the lightemitting elements ED. Similarly, the third electrode RME3_3 may beconnected to the second electrode line RM2 and then separated from thesecond electrode line RM2 in a subsequent process. According to someembodiments, each subpixel PXn may include a first cut area CBA1 and asecond cut area CBA2 respectively positioned on both sides of anemission area EMA in the second direction DR2. The first electrodeRME1_3 and the fourth electrode RME4_3 may be separated from the firstelectrode line RM1 in the first cut area CBA1, and the third electrodeRME3_3 may be separated from the second electrode line RM2 in the secondcut area CBA2. Accordingly, the third electrode RME3_3 and the fourthelectrode RME4_3 might not be directly connected to the circuit layerunder them, except for the first electrode RME1_3 having the firstelectrode contact hole CTD.

The light emitting elements ED may include first light emitting elementsED1 having first ends on the first electrode RME1_3 and second ends onthe third electrode RME3_3, and second light emitting elements ED2having first ends on the fourth electrode RME4_3 and second ends on thesecond electrode RME2_3. The first ends of the first light emittingelements ED1 and the first ends of the second light emitting elementsED2 may face in opposite directions.

Because the display device 10 includes more electrodes RME1_3 throughRME4_3, it may include more contact electrodes CNE1_3 through CNE3_3.

In some embodiments, the contact electrodes CNE1_3 through CNE3_3 mayinclude a first contact electrode CNE1_3 on the first electrode RME1_3,a second contact electrode CNE2_3 on the second electrode RME2_3, and athird contact electrode CNE3_3 on the third electrode RME3_3 and thefourth electrode RME4_3 to surround the second contact electrode CNE2_3.

The first contact electrode CNE1_3 is on the first electrode RME1_3 tocontact the first ends of the first light emitting elements ED1. Thesecond contact electrode CNE2_3 is on the second electrode RME2_3 tocontact the second ends of the second light emitting elements ED2. Thefirst contact electrode CNE1_3 and the second contact electrode CNE2_3may respectively contact the electrodes RME1_3 and RME2_3 connected tothe first transistor T1 and a second voltage wiring VSL.

In each subpixel PXn, the electrodes RME3_3 and RME4_3 not having thefirst and second electrode contact holes CTD and CTS are furtherprovided. They may substantially be electrodes to which an electricalsignal is not directly transmitted from the first transistor T1 or thesecond voltage wiring VSL. However, the third contact electrode CNE3_3may be on the electrodes RME3_3 and RME4_3, and electrical signalstransmitted to the light emitting elements ED1 and ED2 may flow throughthe third contact electrode CNE3_3.

The third contact electrode CNE3_3 may be on the third electrode RME3_3and the fourth electrode RME4_3 and may surround the second contactelectrode CNE2_3. The third contact electrode CNE3_3 may includeportions extending in the second direction DR2 and a portion connectingthese portions and extending in the first direction DR1 so as tosurround the second contact electrode CNE2_3. The portions of the thirdcontact electrode CNE3_3 extending in the second direction DR2 maycontact the third electrode RME3_3 and the fourth electrode RME4_3,respectively. For example, of the third contact electrode CNE3_3, aportion on the third electrode RME3_3 may contact the second ends of thefirst light emitting elements ED1, and a portion on the fourth electrodeRME4_3 may contact the first ends of the second light emitting elementsED2. In some embodiments, the third contact electrode CNE3_3 may contacteach of the third electrode RME3_3 and the fourth electrode RME4_3, anda floating state of the third and fourth electrodes RME3_3 and RME4_3may be prevented or reduced, even if the third and fourth electrodesRME3_3 and RME4_3 are not connected to a third conductive layer.

An electrical signal transmitted from the first contact electrode CNE1_3to the first ends of the first light emitting elements ED1 istransmitted to the third contact electrode CNE3_3 that contacts thesecond ends of the first light emitting elements ED1. The third contactelectrode CNE3_3 may transmit the electrical signal to the first ends ofthe second light emitting elements ED2, and the electrical signal may betransmitted to the second electrode RME2_3 through the second contactelectrode CNE2_3. Accordingly, the electrical signal for light emissionof the light emitting elements ED may be transmitted only to one firstelectrode RME1_3 and one second electrode RME2_3, and the first lightemitting elements ED1 and the second light emitting elements ED2 may beconnected in series to each other through the third contact electrodeCNE3_3.

Although a case where the voltage wirings VDL and VSL and the electrodelines RM1 and RM2 are in each pixel PX has been described in the aboveembodiments, the present disclosure is not limited thereto. According tosome embodiments, in the display device 10, some of the voltage wiringsVDL and VSL and the electrode lines RM1 and RM2 might not be repeatedlyarranged on a pixel-by-pixel basis, but may be alternately arranged. Insome embodiments, pixels PX sharing one voltage wiring VDL and/or VSL,and/or one electrode line RM1 and/or RM2, may be included.

FIGS. 22 through 25 are schematic views illustrating the arrangement ofvoltage wirings VDL and VSL and electrode lines RM1 and RM2 in aplurality of pixels PX of display devices 10_4 through 10_7 according toembodiments. FIGS. 22 through 25 schematically illustrate the pixels PXseparated by the voltage wirings VDL and VSL and the electrode lines RM1and RM2 and the arrangement of electrodes RME1 and RME2 and lightemitting elements ED in subpixels PXn of each pixel PX.

First, referring to FIG. 22, in the display device 10_4 according tosome embodiments, pixels PX in a first pixel column PXC1 and a secondpixel column PXC2 may share the same voltage wiring VDL or VSL. Becausethe pixels PX of the first pixel column PXC1 and the second pixel columnPXC2 adjacent in the first direction DR1 share one voltage wiring VDL orVSL, only one wiring vertical portion VDL_V or VSL_V may be placedbetween them.

In FIG. 22, one first wiring vertical portion VDL_V is between thepixels PX of the first pixel column PXC1 and the second pixel columnPXC2. In some embodiments, only one second wiring vertical portion VSL_Vmay be between different pixel columns PXC. A portion where a firstvoltage wiring VDL is shared will be described below as an example.

Unlike in the example of FIG. 12, the first wiring vertical portionVDL_V and the second wiring vertical portion VSL_V may be alternatelyarranged along the first direction DR1 on a pixel-by-pixel basis. Forexample, only the first wiring vertical portion VDL_V may be between thefirst pixel column PXC1 and the second pixel column PXC2, and only thesecond wiring vertical portion VSL_V may be between the second pixelcolumn PXC2 and another pixel column PXC adjacent to the second pixelcolumn PXC2 in the first direction DR1. The current example is differentfrom the example of FIG. 12 in that pixels PX of pixel columns PXCadjacent in the first direction DR1 share the first wiring verticalportion VDL_V.

As in the example of FIG. 12, pixels PX in the same pixel row PXR mayshare the same wiring horizontal portions VDL_H and VSL_H. However, inthe current example, pixels PX in different pixel columns PXC may sharethe same wiring vertical portion VDL_V or VSL_V. Because in FIG. 22, thepixels PX of the first pixel column PXC1 and the second pixel columnPXC2 share the first wiring vertical portion VDL_V, a first electrodeline RM1 overlapping the first wiring vertical portion VDL_V in thethickness direction may also be shared by the pixels PX of the firstpixel column PXC1 and the second pixel column PXC2. One first electrodestem portion RM1_S or one second electrode stem portion RM2_S may bebetween the first pixel column PXC1 and the second pixel column PXC2,and pixels PX of different pixel columns PXC adjacent in the firstdirection DR1 may share the same electrode stem portion RM1_S or RM2_S.In the pixels PX in the same pixel row PXR, different electrode branchportions RM1_B or RM2_B branching from the same electrode stem portionRM1_S or RM2_S may be provided. In each pixel PX in the first pixelcolumn PXC1, a first electrode branch portion RM1_B branching toward thesecond side of the first direction DR1 and a second electrode branchportion RM2_B branching toward the first side of the first direction DR1may be provided. In each pixel PX in the second pixel column PXC2, afirst electrode branch portion RM1_B branching toward the first side ofthe first direction DR1 and a second electrode branch portion RM2_Bbranching toward the second side of the first direction DR1 may beprovided. Because the electrode branch portions RM1_B and RM2_B indifferent pixel columns PXC extend in different directions, positions ofthe electrodes RME1 and RME2 may also be different in each subpixel PXn.

For example, in first through third pixels PX#1 through PX#3, which arepixels PX in the first pixel column PXC1, a second electrode RME2 may beon a left side of a center of each subpixel PXn, and a first electrodeRME1 may be on a right side of the center of each subpixel PXn, as inthe example of FIG. 12. Light emitting elements ED in the subpixels PXnof the first through third pixels PX#1 through PX#3 may be first lightemitting elements ED1 whose first ends face the first side of the firstdirection DR1. On the other hand, in fourth through sixth pixels PX#4through PX#6, which are pixels PX in the second pixel column PXC2, afirst electrode RME1 may be on a left side of a center of each subpixelPXn, and a second electrode RME2 may be on a right side of the center ofeach subpixel PXn. Light emitting elements ED in the subpixels PXn ofthe fourth through sixth pixels PX#4 through PX#6 may be second lightemitting elements ED2 whose first ends face the second side of the firstdirection DR1. In the display device 10_4 according to some embodiments,because pixels PX of neighboring pixel columns PXC share the voltagewiring VDL or VSL and the electrode line RM1 or RM2, they may includedifferent types of pixels PX#A and PX#B in which the arrangement of theelectrodes RME1 and RME2 and the light emitting elements ED of eachsubpixel PXn is different. For example, the first through third pixelsPX#1 through PX#3 may be first type pixels PX#A, in which the first endsof the light emitting elements ED face the first side of the firstdirection DR1, and the fourth through sixth pixels PX#4 through PX#6 maybe second type pixels PX#B, in which the first ends of the lightemitting elements ED face the second side of the first direction DR1.The first type pixels PX#A and the second type pixels PX#B may besymmetrical to each other in the arrangement of the light emittingelements ED and the electrodes RME1 and RME2 with respect to animaginary line extending in the second direction DR2 between the firsttype pixels PX#A and the second type pixels PX#B.

In the current example, because the voltage wirings VDL and VSL and theelectrode lines RM1 and RM2 are not repeatedly arranged on apixel-by-pixel basis, but are alternately arranged, neighboring pixelsPX may share the voltage wiring VDL or VSL and the electrode line RM1 orRM2. Accordingly, the number of wirings per unit area can be reduced,which is advantageous in implementing an ultra-high resolution displaydevice. Furthermore, because the voltage wirings VDL and VSL and theelectrode lines RM1 and RM2 are alternately arranged, the display device10_4 may include different types of pixels PX#A and PX#B based on thearrangement of the light emitting elements ED and the electrodes RME1and RME2.

Next, referring to FIGS. 23 through 25, in the display devices 10_5through 10_7 according to some embodiments, pixels PX in neighboringpixel rows PXR may share the same voltage wiring VDL or VSL and the sameelectrode line RM1 or RM2. One wiring horizontal portion VDL_H or VDL_Hand one electrode branch portion RM1_B or RM2_B may be shared by pixelsPX in a first pixel row PXR1 and a second pixel row PXR2 adjacent in thesecond direction DR2, and by pixels PX in the second pixel row PXR2 anda third pixel row PXR3 adjacent in the second direction DR2. Therefore,one wiring horizontal portion VDL_H or VDL_H and one electrode branchportion RM1_B or RM2_B may be provided between them. The embodiments ofFIGS. 23 through 25 are different from the example of FIG. 22 in thatneighboring pixel rows PXR are also to share the voltage wiring VDL orVSL and the electrode line RM1 or RM2.

Unlike in the example of FIG. 22, a first wiring horizontal portionVDL_H and a second wiring horizontal portion VDL_H may be alternatelyarranged along the second direction DR2 on a pixel-by-pixel basis. Forexample, only the first wiring horizontal portion VDL_H may be betweenthe first pixel row PXR1 and the second pixel row PXR2, and only thesecond wiring horizontal portion VSL_H may be between the second pixelrow PXR2 and the third pixel row PXR3. Because pixels PX of differentpixel rows PXR share the wiring horizontal portion VDL_H or VSL_H, theymay also share the electrode line RM1 or RM2 overlapping the wiringhorizontal portion VDL_H or VSL_H in the thickness direction.

For example, one first electrode branch portion RM1_B may be between thefirst pixel row PXR1 and the second pixel row PXR2 of each pixel columnPXC, and one second electrode branch portion RM2_B may be between thesecond pixel row PXR2 and the third pixel row PXR3. Pixels PX ofdifferent pixel rows PXR adjacent in the second direction DR2 may sharethe same electrode branch portion RM1_B or RM2_B. However, as in theexample of FIG. 22, different electrode branch portions RM1_B or RM2_Bbranching from the same electrode stem portion RM1_S or RM2_S may beprovided in pixels PX in the same pixel row PXR.

Because pixels PX neighboring in the second direction DR2 share theelectrode branch portion RM1_B or RM2_B, positions of electrodes RME1and RME2 may be different in each subpixel PXn.

First, in the display device 10_5 according to some embodiments of FIG.23, electrodes RME1 or RME2 connected to one electrode branch portionRM1_B or RM2_B and in different pixels PX may be side by side in thesecond direction DR2. For example, first electrodes RME1 in a firstpixel row PXR1 of a first pixel column PXC1 and first electrodes RME1 ina second pixel row PXR2 of the first pixel column PXC1 may lie on thesame lines in the second direction DR2. Accordingly, the firstelectrodes RME1 of a first pixel PX#1 and a second pixel PX#2 may beside by side. Similarly, second electrodes RME2 in the second pixel rowPXR2 of the first pixel column PXC1 and second electrodes RME2 in athird pixel row PXR3 of the first pixel column PXC1 may lie on the samelines in the second direction DR2, and the second electrodes RME2 of thesecond pixel PX#2 and the third pixel PX#3 may be side by side.Electrodes RME1 and RME2 of fourth through sixth pixels PX#4 throughPX#6 may also be arranged in a similar way to the above.

The first pixel PX#1 and the third pixel PX#3 may be first type pixelsPX#A, and the fourth pixel PX#4 and the sixth pixel PX#6 may be secondtype pixels PX#B, as in the example of FIG. 22. However, the secondpixel PX#2 may be different from a first type pixel PX#A. This isbecause while the first electrodes RME1 are on a right side and thesecond electrodes RME2 are on a left side in the second pixel PX#2 sothat first ends of light emitting elements ED face the first side of thefirst direction DR1, the first electrode RME1 is separated from a firstelectrode line RM1 on an upper side of each subpixel PXn, and the secondelectrode RME2 is connected to a second electrode line RM2 on a lowerside of each subpixel PXn. In some embodiments, the fifth pixel PX#5 maybe different from a second type pixel PX#B. This is because while thefirst electrodes RME1 are on the left side and the second electrodesRME2 are on the right side in the fifth pixel PX#5 so that the firstends of the light emitting elements ED face the second side of the firstdirection DR1, the first electrode RME1 is separated from the firstelectrode line RM1 on the upper side of each subpixel PXn, and thesecond electrode RME2 is connected to the second electrode line RM2 onthe lower side of each subpixel PXn.

The display device 10_5 may further include different types of pixelsaccording to the arrangement of the electrode lines RM1 and RM2 from orto which the electrodes RME1 and RME2 are separated or connected, inaddition to the direction in which the first ends of the light emittingelements ED face and the arrangement of the electrodes RME1 and RME2. Insome embodiments, the second pixel PX#2 may be a third type pixel PX#C,and the fifth pixel PX#5 may be a fourth type pixel PX#D. A third typepixel PX#C may be symmetrical to a first type pixel PX#A in thearrangement of the light emitting elements ED and the electrodes RME1and RME2 with respect to an imaginary line extending in the firstdirection DR1 between the third type pixel PX#C and the first type pixelPX#A. In some embodiments, a fourth type pixel PX#D may be symmetricalto a second type pixel PX#B in the arrangement of the light emittingelements ED and the electrodes RME1 and RME2 with respect to animaginary line extending in the first direction DR1 between the fourthtype pixel PX#D and the second type pixel PX#B.

However, the present disclosure is not limited thereto. Even if theelectrodes RME1 or RME2 are separated from or connected to the sameelectrode line RM1 or RM2, they may also be staggered instead of beingarranged side by side.

Referring to FIG. 24, in the display device 10_6, electrodes RME1 orRME2 connected to one electrode branch portion RM1_B or RM2_B and indifferent pixels PX may be staggered in the second direction DR2. Forexample, first electrodes RME1 in a first pixel row PXR1 of a firstpixel column PXC1 may be staggered with respect to first electrodes RME1in a second pixel row PXR2 of the first pixel column PXC1 in the seconddirection DR2, and may lie on the same lines as second electrodes RME2in the second direction DR2. Accordingly, the first electrodes RME1 of afirst pixel PX#1 and the second electrodes RME2 of a second pixel PX#2may be arranged side by side. Similarly, the second electrodes RME2 ofthe second pixel PX#2 and first electrodes RME1 of a third pixel PX#3may be arranged side by side. Electrodes RME1 and RME2 of fourth throughsixth pixels PX#4 through PX#6 may also be arranged in a similar way tothe above.

The first and third pixels PX#1 and PX#3 and the fourth and sixth pixelsPX#4 and PX#6 may respectively be first type pixels PX#A and second typepixels PX#B as in the example of FIG. 23. However, the second pixel PX#2may be a fourth type pixel PX#D, like the fifth pixel PX#5 of FIG. 23,and the fifth pixel PX#5 may be a third type pixel PX#C, like the secondpixel PX#2 of FIG. 23. The current example is different from the exampleof FIG. 23 in the arrangement of the electrodes RME1 and RME2 separatedfrom or connected to electrode lines RM1 and RM2.

Separation and connection positions of the electrodes RME1 and RME2 inneighboring pixel rows PXR are different, even if different electrodebranch portions RM1_B and RM2_B are in neighboring pixel columns PXC,and the arrangement of the electrodes RME1 and RME2 separated from orconnected to the electrode branch portions RM1_B and RM2_B may be thesame.

Referring to FIG. 25, in the display device 10_7, the arrangement offirst and second electrodes RME1 and RME2 of each subpixel PXn in planview may be the same in pixels PX in a first pixel column PXC1 andpixels PX in a second pixel column PXC2. In this case, pixels PX in thesame pixel row PXR may be the same type of pixels even if they are indifferent pixel columns PXC. For example, a first pixel PX#1 and afourth pixel PX#4 in a first pixel row PXR1 may be first type pixelsPX#A. A second pixel PX#2 and a fifth pixel PX#5 in a second pixel rowPXR2 may be fourth type pixels PX#D, and a third pixel PX#3 and a sixthpixel PX#6 in a third pixel row PXR3 may be first type pixels PX#A.

In the display device 10 according to some embodiments, the arrangementof voltage wirings VDL and VSL and electrode lines RM1 and RM2 in a meshstructure may be modified so that neighboring pixels PX can share thesame wiring or line, and different types of pixels PX in which thearrangement of light emitting elements ED and the electrodes RME1 andRME2 is different may be included.

FIG. 26 is a schematic plan view of a plurality of electrodes and aplurality of banks included in one pixel PX of a display device 10_8according to some embodiments. FIG. 27 is a cross-sectional view takenalong line Q9-Q9′ of FIG. 26.

Referring to FIGS. 26 and 27, in the display device 10_8 according tosome embodiments, a first contact electrode CNE1_8 may be directlyconnected to a second capacitive electrode CSE2 or a connected extensionelectrode portion EP. A first electrode RME1 may omit an electrodecontact portion CTP, and the first contact electrode CNE1_8 may includea contact electrode contact portion CN_P. The contact electrode contactportion CN_P may directly contact the extension electrode portion EP orthe second capacitive electrode CSE2 through a first electrode contacthole CTD formed in each subpixel PXn. The current example is differentfrom the example of FIGS. 7 and 8 in that the first electrode RME1 andthe first contact electrode CNE1_8 are electrically connected to a firsttransistor T1 through the contact electrode contact portion CN_P. Otherdetails are the same as those described above, and thus a redundantdescription thereof is not provided.

In a display device according to some embodiments, voltage wirings andelectrode lines are outside of emission areas. Therefore, the electrodelines, and the voltage wirings under the electrode lines, may form anequipotential during a manufacturing process, thereby preventing orreducing the risk of light emitting elements being moved out of place.In some embodiments, in the display device, because a pair of voltagewirings are provided in each pixel, a plurality of subpixels can sharethe same voltage wirings, and the number of wirings per unit area can bereduced, which is advantageous in implementing an ultra-high resolutiondisplay device.

In concluding the detailed description, those skilled in the art willappreciate that many variations and modifications can be made to thedisclosed embodiments without substantially departing from theprinciples of the present disclosure as defined by the following claimsand equivalents thereof. Therefore, the disclosed embodiments of thepresent disclosure are used in a generic and descriptive sense only andnot for purposes of limitation.

What is claimed is:
 1. A display device comprising: a pixel comprisingemission areas; a first voltage wiring and a second voltage wiringoutside the emission areas of the pixel, and extending both in a firstdirection and in a second direction crossing the first direction; firstelectrodes and second electrodes in the emission areas and extending inone direction; light emitting elements on the first electrodes and thesecond electrodes; first contact electrodes contacting the firstelectrodes and the light emitting elements; second contact electrodescontacting the second electrodes and the light emitting elements; and afirst electrode line overlapping the first voltage wiring and beingoutside the emission areas; and a second electrode line overlapping thesecond voltage wiring and being outside the emission areas, wherein thefirst electrodes and the first electrode line are electrically connectedto the first voltage wiring, and wherein the second electrodes and thesecond electrode line are electrically connected to the second voltagewiring.
 2. The display device of claim 1, wherein the first voltagewiring comprises a first wiring horizontal portion extending in thefirst direction, and a first wiring vertical portion extending in thesecond direction, and wherein the second voltage wiring comprises asecond wiring horizontal portion extending in the first direction, and asecond wiring vertical portion extending in the second direction.
 3. Thedisplay device of claim 2, wherein the first wiring vertical portion ison a different conductive layer than the first wiring horizontalportion, and wherein the second wiring vertical portion is on adifferent conductive layer than the second wiring horizontal portion. 4.The display device of claim 3, further comprising: a first wiringcontact hole at an intersection of the first wiring horizontal portionand the first wiring vertical portion; and a second wiring contact holeat an intersection of the second wiring horizontal portion and thesecond wiring vertical portion.
 5. The display device of claim 2,wherein the first wiring vertical portion is on a side of the emissionareas in the first direction, wherein the second wiring vertical portionis on another side of the emission areas in the first direction, whereinthe second wiring horizontal portion is on a side of the emission areasin the second direction, and wherein the first wiring horizontal portionis on another side of the emission areas in the second direction.
 6. Thedisplay device of claim 2, wherein the first electrode line overlaps thefirst wiring vertical portion in a thickness direction of the displaydevice, wherein the second electrode line overlaps the second wiringvertical portion in the thickness direction, and wherein the secondelectrodes are directly connected to the second electrode line.
 7. Thedisplay device of claim 6, wherein the first electrodes and the secondelectrodes extend in the first direction, and wherein the firstelectrodes are spaced apart from the first electrode line, and areelectrically connected to the first voltage wiring through a firstelectrode contact hole.
 8. The display device of claim 6, furthercomprising: a first conductive pattern overlapping the first wiringvertical portion and connected to the first wiring vertical portion; anda second conductive pattern overlapping the second wiring verticalportion and connected to the second wiring vertical portion, wherein thesecond electrode line contacts the second conductive pattern through asecond electrode contact hole overlapping the second conductive pattern,and wherein the first electrode line contacts the first conductivepattern through a third electrode contact hole overlapping the firstconductive pattern.
 9. The display device of claim 6, wherein the firstelectrode line comprises a first electrode stem portion extending in thesecond direction, and a first electrode branch portion branching fromthe first electrode stem portion in the first direction, wherein thesecond electrode line comprises a second electrode stem portionextending in the second direction, and a second electrode branch portionbranching from the second electrode stem portion in the first direction,and wherein the first electrode branch portion and the second electrodebranch portion respectively overlap the first wiring horizontal portionand the second wiring horizontal portion in the thickness direction. 10.The display device of claim 9, wherein the first electrodes and thesecond electrodes extend in the second direction, wherein the secondelectrodes are directly connected to the second electrode branchportion, and wherein the first electrodes are spaced apart from thefirst electrode branch portion.
 11. The display device of claim 1,further comprising cut areas spaced apart from the emission areas in theone direction in which the first electrodes and the second electrodesextend, wherein the first electrodes and the first electrode line arespaced apart with the cut areas therebetween.
 12. The display device ofclaim 1, further comprising: first banks in the emission areas andextending in the one direction in which the first electrodes and thesecond electrodes extend; and a second bank surrounding the emissionareas, wherein the first voltage wiring and the second voltage wiringoverlap the second bank in a thickness direction of the display device.13. The display device of claim 1, wherein the emission areas comprise afirst emission area, a second emission area, and a third emission areaspaced apart from each other, wherein the first electrodes and thesecond electrodes are respectively in the first emission area, thesecond emission area, and the third emission area, and wherein thesecond electrodes that are respectively in the emission areas aredirectly connected to the same second electrode line.
 14. A displaydevice comprising: pixels arranged in a first direction in pixel rows,and in a second direction in pixel columns, the second directioncrossing the first direction, the pixels comprising emission areas; afirst voltage wiring and a second voltage wiring between the pixelcolumns and the pixel rows, and extending in the first direction and thesecond direction; a first electrode line overlapping the first voltagewiring and connected to the first voltage wiring; a second electrodeline overlapping the second voltage wiring and connected to the secondvoltage wiring; first electrodes and second electrodes in the emissionareas of the pixels and extending in one direction; and light emittingelements comprising first ends respectively on the first electrodes, andsecond ends respectively on the second electrodes, wherein the firstelectrodes are spaced apart from the first electrode line, wherein thesecond electrodes are connected to the second electrode line, andwherein the pixels comprise first type pixels in which the first ends ofthe light emitting elements face a first side of the first direction,and wherein the first electrodes are spaced apart from the secondelectrodes in the first direction.
 15. The display device of claim 14,wherein the first type pixels are in the second direction in a firstpixel column, and wherein the pixels further comprise second type pixelsin a second pixel column, in which the first ends of the light emittingelements face a second side of the first direction, the second sidefacing oppositely away from the first side of the first direction, thesecond type pixels being symmetrical to the first type pixels inarrangement of the first electrodes and the second electrodes withrespect to a first imaginary line extending in the second direction. 16.The display device of claim 15, wherein the pixels further comprise:third type pixels in which the first ends of the light emitting elementsface the first side of the first direction, the third type pixels beingsymmetrical to the first type pixels in arrangement of the firstelectrodes and the second electrodes with respect to a second imaginaryline extending in the first direction; and fourth type pixels in whichthe first ends of the light emitting elements face the second side ofthe first direction, the fourth type pixels being symmetrical to thesecond type pixels in arrangement of the first electrodes and the secondelectrodes with respect to the second imaginary line extending in thefirst direction.
 17. The display device of claim 16, wherein the firstelectrodes of the first type pixels and of the second type pixels arerespectively side by side in the second direction with the firstelectrodes of the third type pixels and of the fourth type pixels. 18.The display device of claim 16, wherein the first type pixels and thethird type pixels alternate along the second direction in the firstpixel column, and wherein the second type pixels and the fourth typepixels are alternating along the second direction in the second pixelcolumn.
 19. The display device of claim 16, wherein the first typepixels and the fourth type pixels alternate along the second directionin the first pixel column, and wherein the second type pixels and thethird type pixels alternate along the second direction in the secondpixel column.
 20. The display device of claim 16, wherein the first typepixels and the fourth type pixels alternate along the second directionin the first pixel column and the second pixel column.